Joachim Strömbergson
e4d6781088
Changing non clocked alway assignment to blocking.
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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2025-04-23 16:59:53 +02:00
David Anderson
af8e85b7d2
techlibs/lattice: add missing clock muxes to ECP5 block ram blackboxes
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prjtrellis documentation shows that EBR clock inputs have optional inverters.
The bram techmap outputs those parameters, and nextpnr consumes them. But for
whatever reason, Diamond doesn't include those parameters in its blackbox
models. This makes synth_lattice fail when targeting ECP5 with a design that
maps block RAMs if you include any pass that needs cells_bb_ecp5.v's definitions.
This change fixes up the ECP5 bram blackbox models at generation time, by
adding the missing parameters back in.
Signed-off-by: David Anderson <dave@natulte.net>
2025-04-21 11:57:49 -07:00
Miodrag Milanovic
c343462c16
gatemate: WRITE_THROUGH mode change
2025-04-18 14:16:02 +02:00
Anhijkt
163e339c69
ice40_dsp: add unextend_unsigned function
2025-04-11 19:41:35 +03:00
Anhijkt
4a178d7cff
ice40_dsp: change unextend call condition
2025-04-10 17:42:39 +03:00
Adrien Prost-Boucle
3911a627a8
Clearer diff for the all-x corner case
2025-04-07 07:55:30 +02:00
Adrien Prost-Boucle
7a1729e609
Fix mux xilinx mapping when all inputs are x
2025-04-06 11:43:17 +02:00
Anhijkt
2b3a148fc4
ice40_dsp: fix const handling
2025-04-05 13:46:38 +03:00
Emil J
1b25e1cee0
Merge pull request #4942 from Anhijkt/fix-ice40dsp
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ice40_dsp: fix log_assert issue
2025-03-28 13:32:17 +01:00
YRabbit
c37db637c7
Gowin. Remove unnecessary modules
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Primitives that are not planned for implementation for reasons of
belonging to old unsupported chips or representing composite complex IPs
rather than primitives are removed.
Also latches and large MUXes not planned for implementation.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2025-03-28 06:34:26 +10:00
Scott Ashcroft
04bbd4e7e2
Make all vector-size related integer params in $print sim model signed
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This fixes iverilog crashes on 32-bit, similar to 95944eb
2025-03-25 13:08:49 +00:00
Miodrag Milanović
733487e730
Merge pull request #4950 from pu-cc/gatemate-serdes-update
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gatemate: Add `CC_SERDES` parameters and update port names
2025-03-20 10:52:23 +01:00
Anhijkt
a9d765e11e
ice40_dsp: group empty wires
2025-03-16 15:11:45 +02:00
Anhijkt
725c489c7e
ice40_dsp: fix log_assert issue
2025-03-15 17:11:32 +02:00
Martin Povišer
6da543a61a
Merge pull request #4818 from povik/macc_v2
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Add `$macc_v2`
2025-03-12 22:55:40 +01:00
KrystalDelusion
bf96ed322d
Merge pull request #4827 from aerkiaga/main
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Update ALU MULT mode in gowin to match nextpnr
2025-03-13 10:49:37 +13:00
Martin Povišer
d8a4991289
Merge pull request #4931 from povik/buf-clean
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opt_clean, simplemap: Add `$buf` handling
2025-03-10 15:10:17 +01:00
Martin Povišer
9f7cdd4bd4
Merge pull request #4262 from RoaLogic/master
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MAX10 updates
2025-03-07 19:59:55 +01:00
Martin Povišer
557047fe1e
opt_clean, simplemap: Add $buf handling
2025-03-07 16:08:38 +01:00
N. Engelhardt
268a034b21
Merge pull request #4866 from YosysHQ/ql_ioff
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add IOFF inference for qlf_k6n10f
2025-03-03 14:12:09 +00:00
N. Engelhardt
303a386ecc
create duplicate IOFFs if multiple output ports are connected to the same register
2025-01-31 11:28:57 +01:00
Krystine Sherwin
0ec5f1b756
pmgen: Move passes out of pmgen folder
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- Techlib pmgens are now in relevant techlibs/*.
- `peepopt` pmgens are now in passes/opt.
- `test_pmgen` is still in passes/pmgen.
- Update `Makefile.inc` and `.gitignore` file(s) to match new `*_pm.h` location,
as well as the `#include`s.
- Change default `%_pm.h` make target to `techlibs/%_pm.h` and move it to the
top level Makefile.
- Update pmgen target to use `$(notdir $*)` (where `$*` is the part of the file
name that matched the '%' in the target) instead of `$(subst _pm.h,,$(notdir
$@))`.
2025-01-31 15:18:28 +13:00
N. Engelhardt
25b400982b
detect aliased I/O ports
2025-01-28 17:37:23 +01:00
N. Engelhardt
9da4fe747e
fix bus ioff inference
2025-01-28 11:23:36 +01:00
Martin Povišer
6c76dcec3e
macc_v2: Fix v2 omissions
2025-01-27 13:08:44 +01:00
N. Engelhardt
1cf8e7c7db
add ioff inference for qlf_k6n10f
2025-01-24 21:17:15 +01:00
Martin Povišer
3184b335da
macc_v2: Fix language constructs in simlib model
2025-01-24 13:22:30 +01:00
Martin Povišer
1e8aa56f7f
macc_v2: Init simlib model
2025-01-24 12:38:03 +01:00
Emil J. Tywoniak
a58481e9b7
mark all hash_into methods nodiscard
2025-01-14 12:39:15 +01:00
Emil J
9f7040b3d1
Merge pull request #4683 from keszybz/use-SOURCE_DATE_EPOCH
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Respect $SOURCE_DATE_EPOCH in generate_bram_types_sim.py
2025-01-10 23:43:26 +01:00
Patrick Urban
1fdb2a4511
gatemate: Add CC_SERDES parameters and update port names
2025-01-10 10:25:10 +01:00
Aritz Erkiaga
9a11204329
Update ALU MULT mode in gowin to match nextpnr
2024-12-23 11:12:48 +01:00
Emil J. Tywoniak
b9b9515bb0
hashlib: hash_eat -> hash_into
2024-12-18 15:09:25 +01:00
Emil J. Tywoniak
4e29ec1854
hashlib: acc -> eat
2024-12-18 15:09:25 +01:00
Emil J. Tywoniak
d071489ab1
hashlib: redo interface for flexibility
2024-12-18 14:49:25 +01:00
Miodrag Milanović
f4ddbc3994
Merge pull request #4771 from pepijndevos/famxtra
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gowin: split cells_xtra by family
2024-12-08 19:46:36 +01:00
KrystalDelusion
c96d02b204
Merge pull request #4784 from YosysHQ/krys/reduce_warnings
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Reduce number of warnings
2024-12-05 09:16:06 +13:00
Emil J
61a6567b9f
Merge pull request #4789 from YosysHQ/emil/sklansky-adder
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Add a Sklansky option for `$lcu` mapping
2024-12-03 11:33:13 +01:00
Emil J. Tywoniak
fe64a714a9
techmap: add a Sklansky option for $lcu mapping
2024-12-02 11:34:58 +01:00
Emil J. Tywoniak
ebd7f2b366
techlibs: add _TECHMAP_DO_ to Han-Carlson adder
2024-12-02 09:54:24 +01:00
Krystine Sherwin
1de5d98ae2
Reduce comparisons of size_t and int
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`Const::size()` returns int, so change iterators that use it to `auto` instead of `size_t`.
For cases where size is being explicitly cast to `int`, use the wrapper that we already have instead: `Yosys::GetSize()`.
2024-11-29 12:53:29 +13:00
Emil J. Tywoniak
4bf3677640
techmap: set Han-Carlson adder priority consistent with Kogge-Stone
2024-11-28 23:54:00 +01:00
Emil J. Tywoniak
6c78bd3637
techmap: add a Han-Carlson option for $lcu mapping
2024-11-28 15:33:21 +01:00
Pepijn de Vos
be836f4af3
gowin: split cells_xtra by family
2024-11-26 15:42:22 +01:00
Emil J
88abc4c20f
Merge pull request #4755 from pepijndevos/cells_xtra
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Gowin: add GW2A and GW5A cells
2024-11-20 13:32:30 +01:00
Pepijn de Vos
b8329df1d0
add GW2A and GW5A cells
2024-11-17 20:25:11 +01:00
Patrick Urban
77e1f748a5
gatemate: run simplemap after muxcover to prevent unmapped multiplexers
2024-11-15 09:49:49 +01:00
Zbigniew Jędrzejewski-Szmek
26a3478d8d
Drop timestamp in generate_bram_types_sim.py
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I'm working on build reproducibility of Fedora packages, and this patch fixes
an issue observed in test rebuilds: the timestamp was set to the actual time
of the build, making builds nonreproducible.
Other "Generated by" strings do not include a timestamp, so drop it here too.
2024-10-30 08:47:18 +01:00
Krystine Sherwin
27b8b4e81e
Docs: Fix missing groups
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$lut and $sop were missed in the rebase, and $buf is new to main since the last rebase.
2024-10-15 11:08:30 +13:00
Krystine Sherwin
1513366f21
Docs: Adding mux cell descriptions
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Also making ver2 cell descriptions consistently spaced.
2024-10-15 07:37:34 +13:00
