446 commits

Author	SHA1	Message	Date
Clifford Wolf	c710df181c	Add pmgen "generate" feature ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-08-16 13:26:36 +02:00
Clifford Wolf	4a57b7e1ab	Refactor demo_reduce into test_pmgen ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-08-16 11:47:51 +02:00
Clifford Wolf	016036f247	Add doc for pmgen semioptional statement, Add pmgen changes to CHANGELOG ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-08-15 23:02:37 +02:00
Clifford Wolf	969ab9027a	Update pmgen documentation ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-08-15 22:48:13 +02:00
Clifford Wolf	eb80d3d43f	Change pmgen default rule to reject, switch peepopt behavior to accept ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-08-15 22:47:59 +02:00
Eddie Hung	c320abc3f4	xilinx_dsp to be sensitive to keep attribute	2019-08-15 12:34:11 -07:00
Eddie Hung	96ee7b9cf7	Simplify	2019-08-15 12:30:46 -07:00
Eddie Hung	27d5df9467	ffH -> ffFJKG	2019-08-15 12:19:34 -07:00
Clifford Wolf	03f98d9176	Add demo_reduce pass to demonstrace recursive pattern matching ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-08-15 18:36:39 +02:00
Clifford Wolf	73bf453929	Improvements in pmgen for recursive patterns ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-08-15 18:35:56 +02:00
Eddie Hung	aad97168b0	Fixes for reverting SigSpec helper functions	2019-08-14 10:22:33 -07:00
Eddie Hung	2f04beeeb5	Perform C -> PCIN optimisation after pattern matcher	2019-08-13 17:11:35 -07:00
Eddie Hung	1b0e68db94	Revert changes to RTLIL::SigSpec methods	2019-08-13 17:09:28 -07:00
Eddie Hung	0597a3ea23	Rename to XilinxDspPass	2019-08-13 10:23:07 -07:00
Eddie Hung	12c692f6ed	Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder" ... This reverts commit c851dc1310, reversing changes made to f54bf1631f.	2019-08-12 12:06:45 -07:00
David Shah	f9020ce2b3	Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"	2019-08-10 17:14:48 +01:00
Eddie Hung	ab1d63a565	Check nusers of DSP output, not whole flop	2019-08-09 17:35:13 -07:00
Eddie Hung	3dd3ab98c2	Improve ice40_dsp for non-fully-32-bit adders	2019-08-09 17:23:12 -07:00
Eddie Hung	dfc878deb4	Another filter -> if	2019-08-09 16:23:32 -07:00
Eddie Hung	e83f231927	Cleanup	2019-08-09 15:47:40 -07:00
Eddie Hung	0b5b56c1ec	Pack partial-product adder DSP48E1 packing	2019-08-09 15:19:33 -07:00
Eddie Hung	a002eba14a	Fix check	2019-08-09 14:27:08 -07:00
Eddie Hung	82cbfada1b	Revert "Fix typo" ... This reverts commit e3c39cc450.	2019-08-09 14:14:28 -07:00
Eddie Hung	747690a6df	Remove muxY and ffY for now	2019-08-08 16:33:37 -07:00
Eddie Hung	2c0be7aa5d	Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing	2019-08-08 12:56:05 -07:00
Eddie Hung	07e50b9c25	Only pack registers if {A,B,P}REG = 0, do not pack $dffe	2019-08-08 10:51:19 -07:00
Eddie Hung	911129e3ef	Disable $dffe	2019-08-08 10:44:49 -07:00
Eddie Hung	675c1d4218	Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER	2019-08-07 16:29:38 -07:00
Eddie Hung	fb568ddb4e	Fix compile error	2019-08-07 14:31:55 -07:00
Eddie Hung	d90b8b081a	Do not SigSpec::extract() beyond bounds	2019-08-07 13:58:26 -07:00
Eddie Hung	cdf9c80134	Do not pack registers if (* keep *)	2019-08-07 12:57:10 -07:00
Eddie Hung	c39b1a6fcf	Add comment about supporting $dffe in ice40_dsp	2019-08-01 15:13:18 -07:00
Eddie Hung	ed7540a46f	Pack P register properly	2019-08-01 15:10:43 -07:00
Eddie Hung	e19d33b003	Cope with sign extension in mul2dsp	2019-08-01 12:44:56 -07:00
Eddie Hung	c54a39069d	CO is sign extension only if signed multiplier	2019-08-01 10:00:49 -07:00
Eddie Hung	e3c39cc450	Fix typo	2019-08-01 10:00:01 -07:00
Eddie Hung	e4a638c292	Restore old CO behaviour	2019-07-31 15:45:15 -07:00
Eddie Hung	4c25d1a76f	Pop the CO bit from O	2019-07-26 10:27:30 -07:00
Eddie Hung	c1a05f4557	Allow adders/accumulators with 33 bits using CO output	2019-07-26 10:15:36 -07:00
Eddie Hung	79fd6edc5a	Eliminate warnings by sizing O correctly	2019-07-23 15:13:30 -07:00
Eddie Hung	a37574ccbf	Fix muxAB logic	2019-07-23 14:52:14 -07:00
Eddie Hung	0dd2a125f6	Remove debug print	2019-07-23 14:21:45 -07:00
Eddie Hung	dc0c853abe	Simplify and fix for MACs	2019-07-23 14:20:34 -07:00
Eddie Hung	4f11ff8ebd	Fix typo	2019-07-23 13:58:56 -07:00
Eddie Hung	33c984a044	Fix spacing	2019-07-22 16:37:13 -07:00
Eddie Hung	068617f094	Pack hi and lo registers separately	2019-07-22 16:12:57 -07:00
Eddie Hung	4d71ab384d	Rename according to vendor doc TN1295	2019-07-22 15:08:26 -07:00
Eddie Hung	304cefbbe2	Pack Y register	2019-07-22 15:05:16 -07:00
Eddie Hung	5a14b6e1f6	Pack adders not just accumulators	2019-07-22 13:01:49 -07:00
Eddie Hung	e0720a8018	Restore old ffY behaviour	2019-07-19 22:47:08 -07:00