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Only pack registers if {A,B,P}REG = 0, do not pack $dffe

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This commit is contained in:
Eddie Hung 2019-08-08 10:51:19 -07:00
parent 7160243874
commit 07e50b9c25
1 changed files with 6 additions and 3 deletions
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9
passes/pmgen/xilinx_dsp.pmg
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@ -8,9 +8,10 @@ match dsp
endmatch
match ffA
select ffA->type.in($dff, $dffe)
select ffA->type.in($dff)
// DSP48E1 does not support clock inversion
select param(ffA, \CLK_POLARITY).as_bool()
filter param(dsp, \AREG).as_int() == 0
filter !port(dsp, \A).remove_const().empty()
filter includes(port(ffA, \Q).to_sigbit_set(), port(dsp, \A).remove_const().to_sigbit_set())
optional
@ -22,9 +23,10 @@ code clock
endcode
match ffB
select ffB->type.in($dff, $dffe)
select ffB->type.in($dff)
// DSP48E1 does not support clock inversion
select param(ffB, \CLK_POLARITY).as_bool()
filter param(dsp, \BREG).as_int() == 0
filter !port(dsp, \B).remove_const().empty()
filter includes(port(ffB, \Q).to_sigbit_set(), port(dsp, \B).remove_const().to_sigbit_set())
optional
@ -54,10 +56,11 @@ endcode
match ffP
if !sigPused.empty()
select ffP->type.in($dff, $dffe)
select ffP->type.in($dff)
select nusers(port(ffP, \D)) == 2
// DSP48E1 does not support clock inversion
select param(ffP, \CLK_POLARITY).as_bool()
filter param(dsp, \PREG).as_int() == 0
filter param(ffP, \WIDTH).as_int() >= GetSize(sigPused)
filter includes(port(ffP, \D).to_sigbit_set(), sigPused.to_sigbit_set())
optional