mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 13:29:12 +00:00
Code Activity

Disable $dffe

Browse source
This commit is contained in:
Eddie Hung 2019-08-08 10:44:49 -07:00
parent 57b2e4b9c1
commit 911129e3ef
1 changed files with 8 additions and 8 deletions
Download patch file Download diff file Expand all files Collapse all files

16
passes/pmgen/xilinx_dsp.cc
View file

@ -58,11 +58,11 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm)
SigSpec Q = st.ffA->getPort("\\Q");
A.replace(Q, D);
cell->setPort("\\A", A);
cell->setParam("\\AREG", State::S1);
cell->setParam("\\AREG", 1);
if (st.ffA->type == "$dff")
cell->setPort("\\CEA2", State::S1);
else if (st.ffA->type == "$dffe")
cell->setPort("\\CEA2", st.ffA->getPort("\\EN"));
//else if (st.ffA->type == "$dffe")
// cell->setPort("\\CEA2", st.ffA->getPort("\\EN"));
else log_abort();
}
if (st.ffB) {
@ -71,11 +71,11 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm)
SigSpec Q = st.ffB->getPort("\\Q");
B.replace(Q, D);
cell->setPort("\\B", B);
cell->setParam("\\BREG", State::S1);
cell->setParam("\\BREG", 1);
if (st.ffB->type == "$dff")
cell->setPort("\\CEB2", State::S1);
else if (st.ffB->type == "$dffe")
cell->setPort("\\CEB2", st.ffB->getPort("\\EN"));
//else if (st.ffB->type == "$dffe")
// cell->setPort("\\CEB2", st.ffB->getPort("\\EN"));
else log_abort();
}
if (st.ffP) {
@ -91,8 +91,8 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm)
cell->setParam("\\PREG", State::S1);
if (st.ffP->type == "$dff")
cell->setPort("\\CEP", State::S1);
else if (st.ffP->type == "$dffe")
cell->setPort("\\CEP", st.ffP->getPort("\\EN"));
//else if (st.ffP->type == "$dffe")
// cell->setPort("\\CEP", st.ffP->getPort("\\EN"));
else log_abort();
st.ffP->connections_.at("\\Q").replace(P, pm.module->addWire(NEW_ID, GetSize(P)));