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https://github.com/YosysHQ/yosys
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Add pmgen "generate" feature
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf
parent
4a57b7e1ab
commit
c710df181c
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@ -186,6 +186,9 @@ def process_pmgfile(f, filename):
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block["src"] = "%s:%d" % (filename, linenr)
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block["pattern"] = (current_pattern, current_subpattern)
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block["genargs"] = None
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block["gencode"] = None
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line = line.split()
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assert len(line) == 2
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assert (line[1] not in state_types[current_pattern]) or (state_types[current_pattern][line[1]] == "Cell*")
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@ -236,6 +239,19 @@ def process_pmgfile(f, filename):
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block["semioptional"] = True
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continue
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if a[0] == "generate":
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block["genargs"] = list([int(s) for s in a[1:]])
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block["gencode"] = list()
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assert len(block["genargs"]) < 2
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while True:
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linenr += 1
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l = f.readline()
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assert l != ""
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a = l.split()
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if a[0] == "endmatch": break
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block["gencode"].append(rewrite_cpp(l.rstrip()))
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break
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assert False
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if block["optional"]:
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@ -310,7 +326,17 @@ with open(outfile, "w") as f:
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print("struct {}_pm {{".format(prefix), file=f)
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print(" Module *module;", file=f)
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print(" SigMap sigmap;", file=f)
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print(" std::function<void()> on_accept;".format(prefix), file=f)
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print(" std::function<void()> on_accept;", file=f)
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print(" bool generate_mode;", file=f)
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print("", file=f)
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print(" uint32_t rngseed;", file=f)
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print(" int rng(unsigned int n) {", file=f)
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print(" rngseed ^= rngseed << 13;", file=f)
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print(" rngseed ^= rngseed >> 17;", file=f)
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print(" rngseed ^= rngseed << 5;", file=f)
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print(" return rngseed % n;", file=f)
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print(" }", file=f)
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print("", file=f)
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for index in range(len(blocks)):
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@ -415,7 +441,7 @@ with open(outfile, "w") as f:
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print("", file=f)
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print(" {}_pm(Module *module, const vector<Cell*> &cells) :".format(prefix), file=f)
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print(" module(module), sigmap(module) {", file=f)
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print(" module(module), sigmap(module), generate_mode(false), rngseed(12345678) {", file=f)
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for current_pattern in sorted(patterns.keys()):
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for s, t in sorted(udata_types[current_pattern].items()):
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if t.endswith("*"):
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@ -469,17 +495,15 @@ with open(outfile, "w") as f:
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print(" run_{}([&](){{on_accept_f(*this);}});".format(current_pattern), file=f)
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print(" }", file=f)
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print("", file=f)
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print(" void run_{}(std::function<void(state_{}_t&)> on_accept_f) {{".format(current_pattern, current_pattern), file=f)
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print(" run_{}([&](){{on_accept_f(st_{});}});".format(current_pattern, current_pattern), file=f)
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print(" }", file=f)
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print("", file=f)
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print(" void run_{}() {{".format(current_pattern), file=f)
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print(" run_{}([](){{}});".format(current_pattern, current_pattern), file=f)
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print(" }", file=f)
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print("", file=f)
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for p, s in sorted(subpatterns.keys()):
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print(" void block_subpattern_{}_{}() {{ block_{}(); }}".format(p, s, subpatterns[(p, s)]), file=f)
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if len(subpatterns):
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for p, s in sorted(subpatterns.keys()):
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print(" void block_subpattern_{}_{}() {{ block_{}(); }}".format(p, s, subpatterns[(p, s)]), file=f)
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print("", file=f)
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current_pattern = None
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current_subpattern = None
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@ -611,8 +635,8 @@ with open(outfile, "w") as f:
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print(" std::get<{}>(key) = {};".format(field, entry[2]), file=f)
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print(" const vector<Cell*> &cells = index_{}[key];".format(index), file=f)
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if block["semioptional"]:
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print(" bool found_semioptional_match = false;", file=f)
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if block["semioptional"] or block["genargs"] is not None:
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print(" bool found_any_match = false;", file=f)
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print("", file=f)
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print(" for (int idx = 0; idx < GetSize(cells); idx++) {", file=f)
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@ -620,8 +644,8 @@ with open(outfile, "w") as f:
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print(" if (blacklist_cells.count({})) continue;".format(block["cell"]), file=f)
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for expr in block["filter"]:
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print(" if (!({})) continue;".format(expr), file=f)
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if block["semioptional"]:
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print(" found_semioptional_match = true;", file=f)
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if block["semioptional"] or block["genargs"] is not None:
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print(" found_any_match = true;", file=f)
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print(" block_{}();".format(index+1), file=f)
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print(" if (rollback) {", file=f)
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print(" if (rollback != {}) {{".format(index+1), file=f)
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@ -639,10 +663,17 @@ with open(outfile, "w") as f:
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print(" block_{}();".format(index+1), file=f)
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if block["semioptional"]:
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print(" if (!found_semioptional_match) block_{}();".format(index+1), file=f)
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print(" if (!found_any_match) block_{}();".format(index+1), file=f)
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print(" {} = backup_{};".format(block["cell"], block["cell"]), file=f)
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if block["genargs"] is not None:
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print(" if (generate_mode && !found_any_match) {", file=f)
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if len(block["genargs"]) == 1:
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print(" if (rng(100) >= {}) return;".format(block["genargs"][0]), file=f)
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for line in block["gencode"]:
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print(" " + line, file=f)
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print(" }", file=f)
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else:
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assert False
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@ -23,7 +23,12 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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// for peepopt_pm
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bool did_something;
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#include "passes/pmgen/test_pmgen_pm.h"
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#include "passes/pmgen/ice40_dsp_pm.h"
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#include "passes/pmgen/peepopt_pm.h"
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void reduce_chain(test_pmgen_pm &pm)
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{
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@ -94,6 +99,100 @@ void reduce_tree(test_pmgen_pm &pm)
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log(" -> %s (%s)\n", log_id(c), log_id(c->type));
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}
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#define GENERATE_PATTERN(pmclass, pattern) \
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generate_pattern<pmclass>([](pmclass &pm, std::function<void()> f){ return pm.run_ ## pattern(f); }, #pmclass, #pattern, design)
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void pmtest_addports(Module *module)
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{
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pool<SigBit> driven_bits, used_bits;
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SigMap sigmap(module);
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int icnt = 0, ocnt = 0;
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for (auto cell : module->cells())
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for (auto conn : cell->connections())
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{
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if (cell->input(conn.first))
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for (auto bit : sigmap(conn.second))
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used_bits.insert(bit);
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if (cell->output(conn.first))
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for (auto bit : sigmap(conn.second))
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driven_bits.insert(bit);
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}
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for (auto wire : vector<Wire*>(module->wires()))
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{
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SigSpec ibits, obits;
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for (auto bit : sigmap(wire)) {
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if (!used_bits.count(bit))
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obits.append(bit);
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if (!driven_bits.count(bit))
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ibits.append(bit);
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}
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if (!ibits.empty()) {
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Wire *w = module->addWire(stringf("\\i%d", icnt++), GetSize(ibits));
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w->port_input = true;
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module->connect(ibits, w);
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}
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if (!obits.empty()) {
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Wire *w = module->addWire(stringf("\\o%d", ocnt++), GetSize(obits));
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w->port_output = true;
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module->connect(w, obits);
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}
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}
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module->fixup_ports();
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}
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template <class pm>
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void generate_pattern(std::function<void(pm&,std::function<void()>)> run, const char *pmclass, const char *pattern, Design *design)
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{
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log("Generating \"%s\" patterns for pattern matcher \"%s\".\n", pattern, pmclass);
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int modcnt = 0;
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while (modcnt < 100)
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{
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int submodcnt = 0, itercnt = 0, cellcnt = 0;
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Module *mod = design->addModule(NEW_ID);
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while (submodcnt < 10 && itercnt++ < 1000)
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{
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pm matcher(mod, mod->cells());
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matcher.rng(1);
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matcher.rngseed += modcnt;
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matcher.rng(1);
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matcher.rngseed += submodcnt;
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matcher.rng(1);
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matcher.rngseed += itercnt;
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matcher.rng(1);
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matcher.rngseed += cellcnt;
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matcher.rng(1);
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if (GetSize(mod->cells()) != cellcnt)
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{
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bool found_match = false;
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run(matcher, [&](){ found_match = true; });
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if (found_match) {
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Module *m = design->addModule(stringf("\\pmtest_%s_%s_%05d",
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pmclass, pattern, modcnt++));
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mod->cloneInto(m);
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pmtest_addports(m);
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submodcnt++;
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}
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cellcnt = GetSize(mod->cells());
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}
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matcher.generate_mode = true;
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run(matcher, [](){});
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}
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design->remove(mod);
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}
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}
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struct TestPmgenPass : public Pass {
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TestPmgenPass() : Pass("test_pmgen", "test pass for pmgen") { }
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void help() YS_OVERRIDE
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@ -104,11 +203,18 @@ struct TestPmgenPass : public Pass {
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log("\n");
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log("Demo for recursive pmgen patterns. Map chains of AND/OR/XOR to $reduce_*.\n");
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log("\n");
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log("\n");
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log(" test_pmgen -reduce_tree [options] [selection]\n");
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log("\n");
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log("Demo for recursive pmgen patterns. Map trees of AND/OR/XOR to $reduce_*.\n");
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log("\n");
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log("\n");
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log(" test_pmgen -generate [options] <pattern_name>\n");
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log("\n");
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log("Create modules that match the specified pattern.\n");
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log("\n");
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}
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void execute_reduce_chain(std::vector<std::string> args, RTLIL::Design *design)
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@ -149,6 +255,40 @@ struct TestPmgenPass : public Pass {
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test_pmgen_pm(module, module->selected_cells()).run_reduce(reduce_tree);
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}
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void execute_generate(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header(design, "Executing TEST_PMGEN pass (-generate).\n");
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size_t argidx;
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for (argidx = 2; argidx < args.size(); argidx++)
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{
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// if (args[argidx] == "-singleton") {
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// singleton_mode = true;
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// continue;
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// }
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break;
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}
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if (argidx+1 != args.size())
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log_cmd_error("Expected exactly one pattern.\n");
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string pattern = args[argidx];
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if (pattern == "reduce")
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return GENERATE_PATTERN(test_pmgen_pm, reduce);
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if (pattern == "ice40_dsp")
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return GENERATE_PATTERN(ice40_dsp_pm, ice40_dsp);
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if (pattern == "peepopt-muldiv")
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return GENERATE_PATTERN(peepopt_pm, muldiv);
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if (pattern == "peepopt-shiftmul")
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return GENERATE_PATTERN(peepopt_pm, shiftmul);
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log_cmd_error("Unkown pattern: %s\n", pattern.c_str());
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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if (GetSize(args) > 1)
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@ -157,6 +297,8 @@ struct TestPmgenPass : public Pass {
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return execute_reduce_chain(args, design);
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if (args[1] == "-reduce_tree")
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return execute_reduce_tree(args, design);
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if (args[1] == "-generate")
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return execute_generate(args, design);
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}
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log_cmd_error("Missing or unsupported mode parameter.\n");
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}
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@ -13,6 +13,22 @@ endcode
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match first
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select first->type.in($_AND_, $_OR_, $_XOR_)
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filter !non_first_cells.count(first)
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generate
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SigSpec A = module->addWire(NEW_ID);
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SigSpec B = module->addWire(NEW_ID);
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SigSpec Y = module->addWire(NEW_ID);
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switch (rng(3))
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{
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case 0:
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module->addAndGate(NEW_ID, A, B, Y);
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break;
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case 1:
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module->addOrGate(NEW_ID, A, B, Y);
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break;
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case 2:
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module->addXorGate(NEW_ID, A, B, Y);
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break;
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}
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endmatch
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code
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@ -64,6 +80,12 @@ match next
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select next->type.in($_AND_, $_OR_, $_XOR_)
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index <IdString> next->type === chain.back().first->type
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index <SigSpec> port(next, \Y) === port(chain.back().first, chain.back().second)
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generate 50
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SigSpec A = module->addWire(NEW_ID);
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SigSpec B = module->addWire(NEW_ID);
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SigSpec Y = port(chain.back().first, chain.back().second);
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Cell *c = module->addAndGate(NEW_ID, A, B, Y);
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c->type = chain.back().first->type;
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endmatch
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code
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