1301 commits

Author	SHA1	Message	Date
Clifford Wolf	17372d8abd	Added "abc -luts" option, Improved Xilinx logic mapping	2016-02-01 12:40:32 +01:00
Clifford Wolf	2ee608246f	Re-run ice40_opt in "synth_ice40 -abc2"	2015-12-22 12:19:11 +01:00
Clifford Wolf	3102ffbb83	Improvements in ice40_opt	2015-12-22 12:18:38 +01:00
Clifford Wolf	8bf452c364	Bugfix in ice40_ffinit	2015-12-22 12:18:06 +01:00
Clifford Wolf	ec93d258a4	Improved ice40_ffinit	2015-12-22 11:15:25 +01:00
Clifford Wolf	f1b959dc69	Run opt_const before check in default scripts	2015-12-22 11:15:05 +01:00
Clifford Wolf	494e5f24f9	Added "synth_ice40 -abc2"	2015-12-08 11:16:26 +01:00
Clifford Wolf	4d0a6dac7b	Merge pull request #108 from cseed/master ... Added LO to ICESTORM_LC for LUT cascade route.	2015-12-07 03:32:20 +01:00
Cotton Seed	9f5b6e4cbc	Added LO to ICESTORM_LC for LUT cascade route.	2015-12-06 17:24:48 -05:00
Clifford Wolf	0793f1b196	Added ice40_ffinit pass	2015-11-26 18:11:06 +01:00
Clifford Wolf	8ff229a3ea	Fixed WE/RE usage in iCE40 BRAM mapping	2015-11-24 10:51:34 +01:00
Clifford Wolf	3ad742056b	Fixed iCE40 SB_IO OUTPUT_ENABLE vs. outena_q handling	2015-11-06 17:02:16 +01:00
Clifford Wolf	864808992b	Bugfix in Xilinx LUT mapping	2015-10-30 13:58:03 +01:00
Clifford Wolf	bbcbf739e6	Progress on cell help messages	2015-10-20 16:49:11 +02:00
Clifford Wolf	5d1c0ce7c0	Progress on cell help messages	2015-10-17 02:35:19 +02:00
Clifford Wolf	25c1f6e605	Added "prep" command	2015-10-14 22:46:41 +02:00
Clifford Wolf	87adb523aa	Added more cell descriptions	2015-10-14 20:30:59 +02:00
Clifford Wolf	7d3a3a3173	Added first help messages for cell types	2015-10-14 16:27:42 +02:00
Clifford Wolf	f42218682d	Added examples/ top-level directory	2015-10-13 15:41:20 +02:00
Clifford Wolf	924d9d6e86	Added read-enable to memory model	2015-09-25 12:23:11 +02:00
Clifford Wolf	598a475724	Added nlutmap	2015-09-18 21:57:34 +02:00
Clifford Wolf	745d56149d	Renamed GreenPAK4 cells, improved GP4 DFF mapping	2015-09-18 12:00:37 +02:00
Clifford Wolf	d9cecabb87	Fixed copy&paste typo in synth_greenpak4	2015-09-16 09:39:31 +02:00
Clifford Wolf	c5352f45c3	Added GreenPAK4 skeleton	2015-09-16 09:28:37 +02:00
Clifford Wolf	99ccb3180d	Fixed ice40 handling of negclk RAM40	2015-09-10 17:35:19 +02:00
Clifford Wolf	c475deec6c	Switched to Python 3	2015-08-22 09:59:33 +02:00
Clifford Wolf	9596fe74de	Another bugfix for ice40 and xilinx brams_init make rules	2015-08-16 21:39:34 +02:00
Clifford Wolf	aedcfd6fd3	Fixed Makefile rules for generated share files	2015-08-16 21:15:07 +02:00
Clifford Wolf	d5b1a90b33	Added $tribuf and $_TBUF_ sim models	2015-08-16 13:05:32 +02:00
Clifford Wolf	9c33172ece	Added tribuf command	2015-08-16 12:55:25 +02:00
Clifford Wolf	ff50bc2ac3	Added $tribuf and $_TBUF_ cell types	2015-08-16 12:54:52 +02:00
Larry Doolittle	6c00704a5e	Another block of spelling fixes ... Smaller this time	2015-08-14 23:27:05 +02:00
Clifford Wolf	e4ef000b70	Adjust makefiles to work with out-of-tree builds ... This is based on work done by Larry Doolittle	2015-08-12 15:04:44 +02:00
Clifford Wolf	c43f38c81b	Improved handling of "keep" attributes in hierarchical designs in opt_clean	2015-08-12 14:10:14 +02:00
Marcus Comstedt	c9e56bc428	Added iCE40 WARMBOOT cell	2015-08-06 22:58:17 +02:00
Clifford Wolf	8d6d5c30d9	Added WORDS parameter to $meminit	2015-07-31 10:40:09 +02:00
Clifford Wolf	516e8828f2	Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle)	2015-07-27 22:44:01 +02:00
Clifford Wolf	c6ca4780e2	iCE40 DFF sim models: init Q regs to 0	2015-07-20 13:05:18 +02:00
Clifford Wolf	54588a276a	Avoid tristate warning for blackbox ice40/cells_sim.v	2015-07-18 11:59:04 +02:00
Clifford Wolf	85aaf08e53	Improved liberty file test case	2015-07-06 17:45:56 +02:00
Clifford Wolf	f0c9a099d2	Added "synth -nofsm"	2015-07-02 15:25:38 +02:00
Clifford Wolf	6c84341f22	Fixed trailing whitespaces	2015-07-02 11:14:30 +02:00
Clifford Wolf	df0163cd2b	iCE40: set min bram efficiency to 2%	2015-06-20 09:31:19 +02:00
Clifford Wolf	ed128b82d7	Added "synth -nordff -noalumacc"	2015-06-15 17:07:40 +02:00
Clifford Wolf	9500b564ac	synth_ice40 now flattens by default	2015-06-09 20:28:17 +02:00
Clifford Wolf	09ef279b60	Added iCE40 PLL cells	2015-05-31 13:10:43 +02:00
Clifford Wolf	c329233f0d	Added output args to synth_ice40	2015-05-26 17:08:53 +02:00
Clifford Wolf	313f570fcc	improved ice40 SB_IO sim model	2015-05-23 10:17:03 +02:00
Clifford Wolf	264eb8eb6e	Added ice40 SB_IO sim model	2015-05-23 09:30:24 +02:00
Clifford Wolf	61512b6f41	Verific build fixes	2015-05-17 08:19:52 +02:00