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https://github.com/YosysHQ/yosys
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Added examples/ top-level directory
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Clifford Wolf
parent
f13e387321
commit
f42218682d
17 changed files with 7 additions and 4 deletions
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// test comment
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/* test comment */
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library(demo) {
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cell(BUF) {
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area: 6;
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pin(A) { direction: input; }
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pin(Y) { direction: output;
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function: "A"; }
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}
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cell(NOT) {
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area: 3;
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pin(A) { direction: input; }
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pin(Y) { direction: output;
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function: "A'"; }
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}
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cell(NAND) {
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area: 4;
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pin(A) { direction: input; }
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pin(B) { direction: input; }
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pin(Y) { direction: output;
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function: "(A*B)'"; }
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}
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cell(NOR) {
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area: 4;
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pin(A) { direction: input; }
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pin(B) { direction: input; }
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pin(Y) { direction: output;
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function: "(A+B)'"; }
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}
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cell(DFF) {
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area: 18;
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ff(IQ, IQN) { clocked_on: C;
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next_state: D; }
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pin(C) { direction: input;
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clock: true; }
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pin(D) { direction: input; }
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pin(Q) { direction: output;
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function: "IQ"; }
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}
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cell(DFFSR) {
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area: 18;
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ff("IQ", "IQN") { clocked_on: C;
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next_state: D;
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preset: S;
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clear: R; }
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pin(C) { direction: input;
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clock: true; }
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pin(D) { direction: input; }
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pin(Q) { direction: output;
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function: "IQ"; }
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pin(S) { direction: input; }
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pin(R) { direction: input; }
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; // empty statement
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}
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}
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@ -1,39 +0,0 @@
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.SUBCKT BUF A Y
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X1 A B NOT
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X2 B Y NOT
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.ENDS NOT
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.SUBCKT NOT A Y
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M1 Y A Vdd Vdd cmosp L=1u W=10u
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M2 Y A Vss Vss cmosn L=1u W=10u
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.ENDS NOT
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.SUBCKT NAND A B Y
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M1 Y A Vdd Vdd cmosp L=1u W=10u
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M2 Y B Vdd Vdd cmosp L=1u W=10u
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M3 Y A M34 Vss cmosn L=1u W=10u
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M4 M34 B Vss Vss cmosn L=1u W=10u
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.ENDS NAND
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.SUBCKT NOR A B Y
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M1 Y A M12 Vdd cmosp L=1u W=10u
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M2 M12 B Vdd Vdd cmosp L=1u W=10u
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M3 Y A Vss Vss cmosn L=1u W=10u
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M4 Y B Vss Vss cmosn L=1u W=10u
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.ENDS NOR
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.SUBCKT DLATCH E D Q
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X1 D E S NAND
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X2 nD E R NAND
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X3 S nQ Q NAND
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X4 Q R nQ NAND
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X5 D nD NOT
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.ENDS DLATCH
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.SUBCKT DFF C D Q
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X1 nC D t DLATCH
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X2 C t Q DLATCH
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X3 C nC NOT
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.ENDS DFF
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@ -1,44 +0,0 @@
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module BUF(A, Y);
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input A;
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output Y;
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assign Y = A;
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endmodule
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module NOT(A, Y);
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input A;
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output Y;
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assign Y = ~A;
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endmodule
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module NAND(A, B, Y);
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input A, B;
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output Y;
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assign Y = ~(A & B);
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endmodule
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module NOR(A, B, Y);
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input A, B;
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output Y;
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assign Y = ~(A | B);
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endmodule
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module DFF(C, D, Q);
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input C, D;
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output reg Q;
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always @(posedge C)
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Q <= D;
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endmodule
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module DFFSR(C, D, Q, S, R);
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input C, D, S, R;
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output reg Q;
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always @(posedge C, posedge S, posedge R)
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if (S)
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Q <= 1'b1;
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else if (R)
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Q <= 1'b0;
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else
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Q <= D;
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endmodule
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module counter (clk, rst, en, count);
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input clk, rst, en;
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output reg [2:0] count;
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always @(posedge clk)
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if (rst)
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count <= 3'd0;
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else if (en)
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count <= count + 3'd1;
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endmodule
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@ -1,16 +0,0 @@
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read_verilog counter.v
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read_verilog -lib cmos_cells.v
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proc;; memory;; techmap;;
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dfflibmap -liberty cmos_cells.lib
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abc -liberty cmos_cells.lib;;
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# http://vlsiarch.ecen.okstate.edu/flows/MOSIS_SCMOS/latest/cadence/lib/tsmc025/signalstorm/osu025_stdcells.lib
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# dfflibmap -liberty osu025_stdcells.lib
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# abc -liberty osu025_stdcells.lib;;
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write_verilog synth.v
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write_spice synth.sp
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#!/bin/bash
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set -ex
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../../yosys counter.ys
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ngspice testbench.sp
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@ -1,29 +0,0 @@
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* supply voltages
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.global Vss Vdd
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Vss Vss 0 DC 0
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Vdd Vdd 0 DC 3
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* simple transistor model
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.MODEL cmosn NMOS LEVEL=1 VT0=0.7 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7
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.MODEL cmosp PMOS LEVEL=1 VT0=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8
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* load design and library
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.include synth.sp
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.include cmos_cells.sp
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* input signals
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Vclk clk 0 PULSE(0 3 1 0.1 0.1 0.8 2)
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Vrst rst 0 PULSE(0 3 0.5 0.1 0.1 2.9 40)
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Ven en 0 PULSE(0 3 0.5 0.1 0.1 5.9 8)
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Xuut clk rst en out0 out1 out2 COUNTER
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.tran 0.01 50
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.control
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run
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plot v(clk) v(rst)+5 v(en)+10 v(out0)+20 v(out1)+25 v(out2)+30
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.endc
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.end
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@ -1,16 +0,0 @@
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A simple example design, based on the Digilent BASYS3 board
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===========================================================
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Running Yosys:
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yosys run_yosys.ys
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Running Vivado:
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vivado -nolog -nojournal -mode batch -source run_vivado.tcl
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Programming board:
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vivado -nolog -nojournal -mode batch -source run_prog.tcl
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All of the above:
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bash run.sh
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module example(CLK, LD);
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input CLK;
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output [15:0] LD;
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wire clock;
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reg [15:0] leds;
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BUFG CLK_BUF (.I(CLK), .O(clock));
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OBUF LD_BUF[15:0] (.I(leds), .O(LD));
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parameter COUNTBITS = 26;
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reg [COUNTBITS-1:0] counter;
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always @(posedge CLK) begin
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counter <= counter + 1;
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if (counter[COUNTBITS-1])
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leds <= 16'h8000 >> counter[COUNTBITS-2:COUNTBITS-5];
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else
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leds <= 16'h0001 << counter[COUNTBITS-2:COUNTBITS-5];
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end
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endmodule
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set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN W5 } [get_ports CLK]
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set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN U16 } [get_ports {LD[0]}]
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set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN E19 } [get_ports {LD[1]}]
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set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN U19 } [get_ports {LD[2]}]
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set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN V19 } [get_ports {LD[3]}]
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set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN W18 } [get_ports {LD[4]}]
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set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN U15 } [get_ports {LD[5]}]
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set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN U14 } [get_ports {LD[6]}]
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set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN V14 } [get_ports {LD[7]}]
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set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN V13 } [get_ports {LD[8]}]
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set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN V3 } [get_ports {LD[9]}]
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set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN W3 } [get_ports {LD[10]}]
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set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN U3 } [get_ports {LD[11]}]
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set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN P3 } [get_ports {LD[12]}]
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set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN N3 } [get_ports {LD[13]}]
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set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN P1 } [get_ports {LD[14]}]
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set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN L1 } [get_ports {LD[15]}]
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create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK]
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#!/bin/bash
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yosys run_yosys.ys
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vivado -nolog -nojournal -mode batch -source run_vivado.tcl
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vivado -nolog -nojournal -mode batch -source run_prog.tcl
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connect_hw_server
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open_hw_target [lindex [get_hw_targets] 0]
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set_property PROGRAM.FILE example.bit [lindex [get_hw_devices] 0]
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program_hw_devices [lindex [get_hw_devices] 0]
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@ -1,9 +0,0 @@
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read_xdc example.xdc
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read_edif example.edif
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link_design -part xc7a35tcpg236-1 -top example
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opt_design
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place_design
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route_design
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report_utilization
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report_timing
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write_bitstream -force example.bit
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read_verilog example.v
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synth_xilinx -edif example.edif -top example
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