mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-24 01:25:33 +00:00
Code Activity

Added "abc -luts" option, Improved Xilinx logic mapping

Browse source
This commit is contained in:
Clifford Wolf 2016-02-01 12:40:32 +01:00
parent 9251553592
commit 17372d8abd
2 changed files with 39 additions and 15 deletions
Download patch file Download diff file Expand all files Collapse all files

4
techlibs/xilinx/synth_xilinx.cc
View file

@ -97,7 +97,7 @@ struct SynthXilinxPass : public Pass {
log(" opt -fast\n");
log("\n");
log(" map_luts:\n");
log(" abc -lut 5:8 [-dff]\n");
log(" abc -luts 2:2,3,6:5,10,20 [-dff]\n");
log(" clean\n");
log("\n");
log(" map_cells:\n");
@ -204,7 +204,7 @@ struct SynthXilinxPass : public Pass {
if (check_label(active, run_from, run_to, "map_luts"))
{
Pass::call(design, "abc -lut 6:8" + string(retime ? " -dff" : ""));
Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
Pass::call(design, "clean");
}