mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-27 02:45:52 +00:00
Code Activity

Bugfix in Xilinx LUT mapping

Browse source
This commit is contained in:
Clifford Wolf 2015-10-30 13:58:03 +01:00
parent 1e32e4bdae
commit 864808992b
1 changed files with 1 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

2
techlibs/xilinx/synth_xilinx.cc
View file

@ -204,7 +204,7 @@ struct SynthXilinxPass : public Pass {
if (check_label(active, run_from, run_to, "map_luts"))
{
Pass::call(design, "abc -lut 5:8" + string(retime ? " -dff" : ""));
Pass::call(design, "abc -lut 6:8" + string(retime ? " -dff" : ""));
Pass::call(design, "clean");
}