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Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle)

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Clifford Wolf 2015-07-27 22:44:01 +02:00
parent 4d0ba9b3b2
commit 516e8828f2
1 changed files with 0 additions and 1 deletions
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techlibs/ice40/cells_sim.v
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@ -460,7 +460,6 @@ module SB_RAM40_4K (
if (!WMASK_I[13]) memory[WADDR[7:0]][13] <= WDATA_I[13];
if (!WMASK_I[14]) memory[WADDR[7:0]][14] <= WDATA_I[14];
if (!WMASK_I[15]) memory[WADDR[7:0]][15] <= WDATA_I[15];
if (!WMASK_I[16]) memory[WADDR[7:0]][16] <= WDATA_I[16];
end
end