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Code Activity
9492 commits 96 branches 53 tags 45 MiB
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3165 commits

Author SHA1 Message Date
Alberto Gonzalez
e173291649
techmap: Replace naughty const_cast<>()s. 
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
 2020-05-14 20:06:55 +00:00
Alberto Gonzalez
97fd304cbe
techmap: Replace pseudo-private member usage with the range accessor function and some naughty const_cast<>()s. 2020-05-14 20:06:55 +00:00
Eddie Hung
36bb201dd9
techmap: sort celltypeMap as it determines techmap order 2020-05-14 20:06:55 +00:00
Alberto Gonzalez
ce62d0751a
Replace std::sets using custom comparators with pool. 
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
 2020-05-14 20:06:55 +00:00
Eddie Hung
dabeb1e8a1
techmap: prefix special wires with backslash for use as IdString 2020-05-14 20:06:55 +00:00
Alberto Gonzalez
bd54d67ad4
Further clean up passes/techmap/techmap.cc. 
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
 2020-05-14 20:06:54 +00:00
Alberto Gonzalez
982562ff13
Use emplace() for more efficient insertion into various dicts. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez
c658d9d59d
Build constant bits directly rather than constructing an object and copying its bits. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez
f235f212ea
Replace std::set with pool for cell_to_inbit and outbit_to_cell. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez
6294621825
Use emplace() rather than insert(). 2020-05-14 20:06:54 +00:00
Alberto Gonzalez
dfcb936cd5
Clean up pseudo-private member usage and ensure range iteration uses references where possible to avoid unnecessary copies. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez
a4755c50c3
Clean up extraneous buffer. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez
7857782575
Replace std::map with dict for unique_bit_id. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez
6d64d768b0
Replace std::map with dict for port_new2old_map, port_connmap, and cellbits_to_tplbits. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez
5cb4ae4666
Replace std::map with dict for connbits_map, cell_to_inbit, and outbit_to_cell. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez
c43017fc08
Replace std::map with dict for TechmapWires type. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez
644e55b3d3
Replace std::map with dict for celltypeMap. 2020-05-14 20:06:53 +00:00
Alberto Gonzalez
67f4046c05
Replace std::set with pool for handled_cells and techmap_wire_names. 2020-05-14 20:06:53 +00:00
Alberto Gonzalez
64c16f8c13
Replace std::map with dict for positional_ports. 2020-05-14 20:06:53 +00:00
Alberto Gonzalez
2fb4931e5b
Add specialized hash() for type dict and use a dict instead of a std::map for techmap_cache and techmap_do_cache. 2020-05-14 20:06:53 +00:00
Alberto Gonzalez
437f3fb342
Replace std::map with dict for simplemap_mappers. 2020-05-14 20:06:53 +00:00
Alberto Gonzalez
99b586b283
Use nullptr instead of NULL in passes/techmap/techmap.cc. 2020-05-14 20:06:53 +00:00
Alberto Gonzalez
5f7f213c7f
Replace std::string and RTLIL::IdString with IdString in passes/techmap/techmap.cc. 
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
 2020-05-14 20:06:53 +00:00
Alberto Gonzalez
e49fdee404
Do not modify design modules while iterating over modules(). 
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
 2020-05-14 20:06:53 +00:00
Alberto Gonzalez
985a29ff3b
Clean up pseudo-private member usage, superfluous std::vector instantiation, and RTLIL::id2cstr() usage in passes/techmap/techmap.cc. 2020-05-14 20:06:53 +00:00
Claire Wolf
5c82c19b4b
Merge pull request from YosysHQ/claire/fixoptalu 
Fix the other "opt_expr -fine" bug introduced in 213a89558
 2020-05-03 11:56:29 +02:00
Claire Wolf
2285cf1219 Fix the other "opt_expr -fine" bug introduced in 213a89558 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-02 21:50:43 +02:00
Eddie Hung
da7da44919 abc9_ops: -reintegrate to be sensitive to start_offset too 2020-05-02 11:19:04 -07:00
Claire Wolf
ca3fc3c882
Merge pull request from YosysHQ/claire/fixopt 
Fix "opt_expr -fine" bug introduced in 213a89558
 2020-05-02 11:20:02 +02:00
Claire Wolf
8ee32adac3 Fix "opt_expr -fine" bug introduced in 213a89558 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-01 20:12:16 +02:00
whitequark
b43c282e4e Add WASI platform support. 
This includes the following significant changes:
  * Patching ezsat and minisat to disable resource limiting code
    on WASM/WASI, since the POSIX functions they use are unavailable.
  * Adding a new definition, YOSYS_DISABLE_SPAWN, present if platform
    does not support spawning subprocesses (i.e. Emscripten or WASI).
    This definition hides the definition of `run_command()`.
  * Adding a new Makefile flag, DISABLE_SPAWN, present in the same
    condition. This flag disables all passes that require spawning
    subprocesses for their function.
 2020-04-30 18:56:25 +00:00
Eddie Hung
56dd036b97 bugpoint: improve messaging 2020-04-24 13:41:19 -07:00
Eddie Hung
e602184856 bugpoint: (* keep *) to (* bugpoint_keep *); also apply to modules/cells 2020-04-24 13:26:04 -07:00
Eddie Hung
4bfe6ebea9 bugpoint: skip ports with (* keep *) on; add header 2020-04-24 11:17:09 -07:00
Eddie Hung
bf021a0e1f bugpoint: improve help text 2020-04-23 12:16:55 -07:00
Eddie Hung
b048afc3a6
Merge pull request from YosysHQ/eddie/abc9_disable_mfs 
abc9: tolerate &mfs failure by writing output file before calling it (and using that if it fails)
 2020-04-23 06:43:30 -07:00
Claire Wolf
dc9a72bc8d
Merge pull request from boqwxp/qbfsat_anyconst_sourcelocs 
qbfsat: Make hole name recovery from source locations more robust.
 2020-04-23 11:34:19 +02:00
Claire Wolf
1797c574da
Merge pull request from boqwxp/qbfsat 
qbfsat: Add `-assume-negative-polarity` option.
 2020-04-23 11:33:54 +02:00
Alberto Gonzalez
4ee8452d34
qbfsat: Make hole name recovery more robust. Allow multiple cell types to share the same source location as long as only one $anyconst or $anyseq has that location. 2020-04-23 05:45:44 +00:00
Alberto Gonzalez
7369e6b26b
qbfsat: Add -assume-negative-polarity option. 2020-04-23 04:06:15 +00:00
Eddie Hung
592baebd22 xilinx: xilinx_dsp_cascade to check CREG for DSP48E1 only 2020-04-22 17:43:25 -07:00
Eddie Hung
fa9df06c9d
Merge pull request from YosysHQ/eddie/select_blackbox 
select: do not select inside black-/white- boxes unless '=' prefix used
 2020-04-22 15:35:05 -07:00
Claire Wolf
beb9e4b299
Update passes/cmds/select.cc 
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
 2020-04-22 21:31:32 +02:00
Eddie Hung
7f33a0294b Cleanup use of hard-coded default parameters in light of 2020-04-22 12:02:30 -07:00
Eddie Hung
eaa5a3e786 select: do not select black/white boxes by default, '=' prefix to do so 2020-04-22 10:15:56 -07:00
Eddie Hung
28623f19ee
Merge pull request from YosysHQ/eddie/design_import 
design: -import to not count black/white-boxes as candidates for top
 2020-04-22 09:32:13 -07:00
Claire Wolf
c32b4bded5
Merge pull request from YosysHQ/dave/fix-sim-const 
sim: Fix handling of constant-connected cell inputs at startup
 2020-04-22 16:57:34 +02:00
Marcelina Kościelnicka
cd82afb740 bugpoint: Don't remove modules or cells while iterating over them. 
Reported by @ZirconiumX.
 2020-04-22 00:09:01 +02:00
Marcelina Kościelnicka
846c79b312 hierarchy: Convert positional parameters to named. 
Fixes .
 2020-04-21 19:09:00 +02:00
Claire Wolf
d834cc7afb Add '=' selection pattern prefix for non-blackbox only patterns 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-04-21 14:23:24 +02:00