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https://github.com/YosysHQ/yosys
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Add specialized hash()
for type dict
and use a dict
instead of a std::map
for techmap_cache
and techmap_do_cache
.
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parent
437f3fb342
commit
2fb4931e5b
3 changed files with 25 additions and 10 deletions
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@ -63,8 +63,8 @@ void apply_prefix(IdString prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
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struct TechmapWorker
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{
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dict<IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> simplemap_mappers;
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std::map<std::pair<IdString, std::map<IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
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std::map<RTLIL::Module*, bool> techmap_do_cache;
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dict<std::pair<IdString, dict<IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
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dict<RTLIL::Module*, bool> techmap_do_cache;
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std::set<RTLIL::Module*, IdString::compare_ptr_by_name<RTLIL::Module>> module_queue;
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dict<Module*, SigMap> sigmaps;
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@ -568,7 +568,7 @@ struct TechmapWorker
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{
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IdString derived_name = tpl_name;
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RTLIL::Module *tpl = map->module(tpl_name);
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std::map<IdString, RTLIL::Const> parameters(cell->parameters.begin(), cell->parameters.end());
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dict<IdString, RTLIL::Const> parameters(cell->parameters.begin(), cell->parameters.end());
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if (tpl->get_blackbox_attribute(ignore_wb))
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continue;
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@ -778,7 +778,7 @@ struct TechmapWorker
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use_wrapper_tpl:;
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// do not register techmap_wrap modules with techmap_cache
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} else {
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std::pair<IdString, std::map<IdString, RTLIL::Const>> key(tpl_name, parameters);
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std::pair<IdString, dict<IdString, RTLIL::Const>> key(tpl_name, parameters);
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if (techmap_cache.count(key) > 0) {
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tpl = techmap_cache[key];
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} else {
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