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9492 commits

Author SHA1 Message Date
Alberto Gonzalez 6eea4b3d79
kernel: Try an order-independent approach to hashing dict.
Co-Authored-By: David Shah <dave@ds0.me>
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-05-19 23:32:53 +00:00
Alberto Gonzalez 976edb7597
kernel: Ensure dict always hashes to the same value given the same contents. 2020-05-14 20:06:55 +00:00
Alberto Gonzalez 35b94d1f66
kernel: Re-implement dict hash code as a dict member function instead of a specialized template for hash_ops. 2020-05-14 20:06:55 +00:00
Alberto Gonzalez e173291649
techmap: Replace naughty const_cast<>()s.
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-05-14 20:06:55 +00:00
Alberto Gonzalez 97fd304cbe
techmap: Replace pseudo-private member usage with the range accessor function and some naughty const_cast<>()s. 2020-05-14 20:06:55 +00:00
Eddie Hung 36bb201dd9
techmap: sort celltypeMap as it determines techmap order 2020-05-14 20:06:55 +00:00
Alberto Gonzalez ce62d0751a
Replace std::sets using custom comparators with pool.
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-05-14 20:06:55 +00:00
Eddie Hung dabeb1e8a1
techmap: prefix special wires with backslash for use as IdString 2020-05-14 20:06:55 +00:00
Alberto Gonzalez bd54d67ad4
Further clean up passes/techmap/techmap.cc.
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-05-14 20:06:54 +00:00
Alberto Gonzalez 982562ff13
Use emplace() for more efficient insertion into various dicts. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez c658d9d59d
Build constant bits directly rather than constructing an object and copying its bits. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez f235f212ea
Replace std::set with pool for cell_to_inbit and outbit_to_cell. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez 6294621825
Use emplace() rather than insert(). 2020-05-14 20:06:54 +00:00
Alberto Gonzalez dfcb936cd5
Clean up pseudo-private member usage and ensure range iteration uses references where possible to avoid unnecessary copies. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez a4755c50c3
Clean up extraneous buffer. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez 7857782575
Replace std::map with dict for unique_bit_id. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez 6d64d768b0
Replace std::map with dict for port_new2old_map, port_connmap, and cellbits_to_tplbits. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez 5cb4ae4666
Replace std::map with dict for connbits_map, cell_to_inbit, and outbit_to_cell. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez c43017fc08
Replace std::map with dict for TechmapWires type. 2020-05-14 20:06:54 +00:00
Alberto Gonzalez 644e55b3d3
Replace std::map with dict for celltypeMap. 2020-05-14 20:06:53 +00:00
Alberto Gonzalez 67f4046c05
Replace std::set with pool for handled_cells and techmap_wire_names. 2020-05-14 20:06:53 +00:00
Alberto Gonzalez 64c16f8c13
Replace std::map with dict for positional_ports. 2020-05-14 20:06:53 +00:00
Alberto Gonzalez 2fb4931e5b
Add specialized hash() for type dict and use a dict instead of a std::map for techmap_cache and techmap_do_cache. 2020-05-14 20:06:53 +00:00
Alberto Gonzalez 437f3fb342
Replace std::map with dict for simplemap_mappers. 2020-05-14 20:06:53 +00:00
Alberto Gonzalez 99b586b283
Use nullptr instead of NULL in passes/techmap/techmap.cc. 2020-05-14 20:06:53 +00:00
Alberto Gonzalez 5f7f213c7f
Replace std::string and RTLIL::IdString with IdString in passes/techmap/techmap.cc.
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-05-14 20:06:53 +00:00
Alberto Gonzalez e49fdee404
Do not modify design modules while iterating over modules().
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-05-14 20:06:53 +00:00
Alberto Gonzalez 985a29ff3b
Clean up pseudo-private member usage, superfluous std::vector instantiation, and RTLIL::id2cstr() usage in passes/techmap/techmap.cc. 2020-05-14 20:06:53 +00:00
Eddie Hung 283b1130a6
Merge pull request #2025 from YosysHQ/eddie/frontend_cleanup
frontend: cleanup to use more ID::*, more dict<> instead of map<>
2020-05-05 07:59:40 -07:00
whitequark ae409d4d81
Merge pull request #2012 from whitequark/fix-wasi-abc-build
Fix WASI builds with abc enabled
2020-05-05 14:03:40 +00:00
Eddie Hung 5fa06e4894
Merge pull request #2026 from YosysHQ/eddie/scratchpad_abc9_W
synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpad
2020-05-05 06:49:36 -07:00
Eddie Hung 7a62ee57b4
Merge pull request #2024 from YosysHQ/eddie/primitive_src
verilog: set src attribute for primitives
2020-05-05 06:49:18 -07:00
Eddie Hung 99aff5a0f9
Merge pull request #2023 from YosysHQ/eddie/specify_src
verilog: fix specify src attribute
2020-05-05 06:49:06 -07:00
Eddie Hung e6b55e8b38 synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpad 2020-05-04 11:44:00 -07:00
Eddie Hung eb5eb60fd4 verilog: fix specify src attribute 2020-05-04 10:53:06 -07:00
Eddie Hung 22bf22fab4 frontend: cleanup to use more ID::*, more dict<> instead of map<> 2020-05-04 10:48:37 -07:00
Eddie Hung eca9fc01a7 verilog: set src attribute for primitives 2020-05-04 10:22:05 -07:00
Eddie Hung ad8e7878f6 tests: add tests for primitives' src 2020-05-04 10:21:47 -07:00
Eddie Hung 584780d776
Merge pull request #1996 from boqwxp/rtlil_source_locations
frontend: Include complete source location instead of just `location.first_line` in `frontends/ast/genrtlil.cc`.
2020-05-04 08:58:50 -07:00
whitequark d1c8837572
Merge pull request #2000 from whitequark/log_error-trap
kernel: Trap in `log_error()` when a debugger is attached
2020-05-03 16:19:42 +00:00
whitequark e9f2d3f009 kernel: Trap in log_error() when a debugger is attached.
The workflow of debugging fatal pass errors in Yosys is flawed in
three ways:
 1. Running Yosys under a debugger is sufficient for the debugger
    to catch some fatal errors (segfaults, aborts, STL exceptions)
    but not others (`log_error()`, `log_cmd_error()`). This is
    neither obvious nor easy to remember.
 2. To catch Yosys-specific fatal errors, it is necessary to set
    a breakpoint at `logv_error_with_prefix()`, or at least,
    `logv_error()`. This is neither obvious nor easy to remember,
    and GDB's autocomplete takes many seconds to suggest function
    names due to the large amount of symbols in Yosys.
 3. If a breakpoint is not set and Yosys encounters with such
    a fatal error, the process terminates. When debugging a crash
    that takes a long time to reproduce (or a nondeterministic crash)
    this can waste a significant amount of time.

To solve this problem, add a macro `YS_DEBUGTRAP` that acts as a hard
breakpoint (if available), and a macro `YS_DEBUGTRAP_IF_DEBUGGING`
that acts as a hard breakpoint only if debugger is present.

Then, use `YS_DEBUGTRAP_IF_DEBUGGING` in `logv_error_with_prefix()`
to obviate the need for a breakpoint on nearly every platform.

Co-Authored-By: Alberto Gonzalez <boqwxp@airmail.cc>
2020-05-03 12:02:34 +00:00
Claire Wolf 5c82c19b4b
Merge pull request #2014 from YosysHQ/claire/fixoptalu
Fix the other "opt_expr -fine" bug introduced in 213a89558
2020-05-03 11:56:29 +02:00
Eddie Hung db13852ed6 test: add test for #2014 2020-05-02 14:22:37 -07:00
Eddie Hung 7360155459
Merge pull request #2013 from YosysHQ/eddie/aiger_fixes
aiger: fixes for ports that have start_offset != 0
2020-05-02 14:16:10 -07:00
Claire Wolf 2285cf1219 Fix the other "opt_expr -fine" bug introduced in 213a89558
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 21:50:43 +02:00
Eddie Hung da7da44919 abc9_ops: -reintegrate to be sensitive to start_offset too 2020-05-02 11:19:04 -07:00
Eddie Hung 2e78daf1ca tests: aiger test for wire->start_offset != 0 2020-05-02 10:00:32 -07:00
Eddie Hung a0afa1787e aiger: fixes for ports that have start_offset != 0 2020-05-02 10:00:32 -07:00
Claire Wolf ca3fc3c882
Merge pull request #2010 from YosysHQ/claire/fixopt
Fix "opt_expr -fine" bug introduced in 213a89558
2020-05-02 11:20:02 +02:00
whitequark ff7a8d0e1e Update ABC to include WASI support fixes. 2020-05-02 00:18:33 +00:00