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	Replace std::sets using custom comparators with pool.
				
					
				
			Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
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					 1 changed files with 4 additions and 4 deletions
				
			
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			@ -65,7 +65,7 @@ struct TechmapWorker
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	dict<IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> simplemap_mappers;
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	dict<std::pair<IdString, dict<IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
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	dict<RTLIL::Module*, bool> techmap_do_cache;
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	std::set<RTLIL::Module*, IdString::compare_ptr_by_name<RTLIL::Module>> module_queue;
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	pool<RTLIL::Module*> module_queue;
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	dict<Module*, SigMap> sigmaps;
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	pool<IdString> flatten_do_list;
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			@ -465,7 +465,7 @@ struct TechmapWorker
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	}
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	bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, pool<RTLIL::Cell*> &handled_cells,
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			const dict<IdString, std::set<IdString, RTLIL::sort_by_id_str>> &celltypeMap, bool in_recursion)
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			const dict<IdString, pool<IdString>> &celltypeMap, bool in_recursion)
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	{
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		std::string mapmsg_prefix = in_recursion ? "Recursively mapping" : "Mapping";
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			@ -1305,7 +1305,7 @@ struct TechmapPass : public Pass {
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		log_header(design, "Continuing TECHMAP pass.\n");
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		dict<IdString, std::set<IdString, RTLIL::sort_by_id_str>> celltypeMap;
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		dict<IdString, pool<IdString>> celltypeMap;
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		for (auto module : map->modules()) {
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			if (module->attributes.count(ID::techmap_celltype) && !module->attributes.at(ID::techmap_celltype).bits.empty()) {
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				char *p = strdup(module->attributes.at(ID::techmap_celltype).decode_string().c_str());
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			@ -1386,7 +1386,7 @@ struct FlattenPass : public Pass {
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		extra_args(args, argidx, design);
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		dict<IdString, std::set<IdString, RTLIL::sort_by_id_str>> celltypeMap;
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		dict<IdString, pool<IdString>> celltypeMap;
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		for (auto module : design->modules())
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			celltypeMap[module->name].insert(module->name);
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