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Replace std::map with dict for celltypeMap.

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This commit is contained in:
Alberto Gonzalez 2020-04-19 22:32:28 +00:00
parent 67f4046c05
commit 644e55b3d3
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GPG key ID: 8395A8BA109708B2
1 changed files with 3 additions and 3 deletions
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6
passes/techmap/techmap.cc
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@ -464,7 +464,7 @@ struct TechmapWorker
}
bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, pool<RTLIL::Cell*> &handled_cells,
const std::map<IdString, std::set<IdString, RTLIL::sort_by_id_str>> &celltypeMap, bool in_recursion)
const dict<IdString, std::set<IdString, RTLIL::sort_by_id_str>> &celltypeMap, bool in_recursion)
{
std::string mapmsg_prefix = in_recursion ? "Recursively mapping" : "Mapping";
@ -1300,7 +1300,7 @@ struct TechmapPass : public Pass {
log_header(design, "Continuing TECHMAP pass.\n");
std::map<IdString, std::set<IdString, RTLIL::sort_by_id_str>> celltypeMap;
dict<IdString, std::set<IdString, RTLIL::sort_by_id_str>> celltypeMap;
for (auto module : map->modules()) {
if (module->attributes.count(ID::techmap_celltype) && !module->attributes.at(ID::techmap_celltype).bits.empty()) {
char *p = strdup(module->attributes.at(ID::techmap_celltype).decode_string().c_str());
@ -1381,7 +1381,7 @@ struct FlattenPass : public Pass {
extra_args(args, argidx, design);
std::map<IdString, std::set<IdString, RTLIL::sort_by_id_str>> celltypeMap;
dict<IdString, std::set<IdString, RTLIL::sort_by_id_str>> celltypeMap;
for (auto module : design->modules())
celltypeMap[module->name].insert(module->name);