mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 05:19:11 +00:00
Code Activity

Replace std::map with dict for connbits_map, cell_to_inbit, and outbit_to_cell.

Browse source
This commit is contained in:
Alberto Gonzalez 2020-04-19 22:38:10 +00:00
parent c43017fc08
commit 5cb4ae4666
No known key found for this signature in database
GPG key ID: 8395A8BA109708B2
1 changed files with 3 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

6
passes/techmap/techmap.cc
View file

@ -101,7 +101,7 @@ struct TechmapWorker
std::string constmap_tpl_name(SigMap &sigmap, RTLIL::Module *tpl, RTLIL::Cell *cell, bool verbose)
{
std::string constmap_info;
std::map<RTLIL::SigBit, std::pair<IdString, int>> connbits_map;
dict<RTLIL::SigBit, std::pair<IdString, int>> connbits_map;
for (auto conn : cell->connections())
for (int i = 0; i < GetSize(conn.second); i++) {
@ -490,8 +490,8 @@ struct TechmapWorker
}
TopoSort<RTLIL::Cell*, IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit;
std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell;
dict<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit;
dict<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell;
for (auto cell : module->selected_cells())
{