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Author SHA1 Message Date
Akash Levy
a022ca524d Fix flaky opt_priokey -strict and cover binary exclusive scan
ASLR-dependent ConstEval seeding let E4 miss OOR counterexamples; use a
deterministic seed and force OOR key collisions. Add I9 (NB=12) for the
thermometer fallback path Greptile flagged.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-07-08 23:20:22 -07:00
Akash Levy
665bd1099a opt_first_fit_alloc updates + tests + some nice refactoring 2026-07-08 22:33:13 -07:00
Akash Levy
945e4a403b tests/opt: add generalization coverage for the QoR pattern passes
Prove the three pattern detectors work on unseen inputs, not just the RTL
they were derived from. Because detection is functional (ConstEval
fingerprinting over the reachable input space), correctness is established
per case with equiv_opt -assert (full) or a SAT miter clamped to the
reachable range (non-power-of-two), and detection is confirmed with a
w:*tag* probe.

opt_priokey:
  D1-D3  spelling variants (explicit shift-or set, compound derived guard,
         accumulator also exported) -- all fire and prove equivalent.
  E1-E2  parameter sweep P=2..8, S=4..32.
  E3     non-power-of-two S=12 reachable-range equivalence via SAT miter.
  E4     same shape under -strict declines to rewrite (formal-flow safety).
  F1-F2  near-miss negatives (clear accumulator, multi-hot set) -> no rewrite.

opt_prienc (round-robin):
  RR4-RR5 DEPTH sweep 8/32, full sequential equivalence.
  RR6     non-power-of-two DEPTH=7 reachable-range equivalence (SAT miter).
  RR7     an entirely different spelling (upward wrap-scan, first-hit) of the
          same arbiter -- fires and proves equivalent.
  RR8     fixed-priority (no rotating pointer) negative.

opt_first_fit_alloc (coalesce):
  H1      inline same-category compare (no precomputed matrix) spelling.
  H2      different slot/field shape (N=8, NB=8, W=3).

All new cases pass locally; they avoid brittle exact cell-count asserts so
they are robust to upstream optimization drift.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-07-06 22:05:50 -07:00
Akash Levy
00e48706df opt: recognize three QoR logic-depth patterns
Extend two existing opt passes and add one new pass to collapse
serial/dynamic-index structures that were leaving high logic depth:

- opt_first_fit_alloc: recognize the "coalesce-matrix" first-fit
  allocator variant (same_cat[i][k] coalescing gated on the leader's
  enable, driven from a raw input enable). Rewrite both the lane_slot
  allocation and the xbar field gather from one shared log-depth scan.

- opt_prienc: detect round-robin / rotated-priority scans (req scanned
  from idx_last downward with wraparound) and rewrite the depth-N
  idx--/req[idx] mux chain to rotate -> log-depth priority-encode ->
  unrotate.

- opt_priokey (new): recognize priority-by-key one-hot accumulators and
  replace each dynamic taken[key] read ($shiftx/$bmux) with the
  equivalent pairwise-key-compare reduction, dropping the wide dynamic
  indexing. Supports -strict for full-key-range formal validation.

Each includes self-contained tests (equiv_opt / sat -prove-asserts,
mux-bound and negative cases) in tests/opt/.

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-07-06 12:56:38 -07:00
Akash Levy
a2e38e2022 Merge from upstream 2026-07-06 07:47:32 -07:00
Akash Levy
3783a820ee Merge remote-tracking branch 'upstream' into merge3 2026-06-25 04:51:46 -07:00
Miodrag Milanovic
a689342207 Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
Miodrag Milanovic
48a3dcc02a End of file fix 2026-06-23 07:23:41 +02:00
Mohamed Gaber
0e7671c1b3 Merge remote-tracking branch 'origin/main' into update_from_upstream 2026-06-21 15:07:32 +03:00
Akash Levy
dc995eba98 opt_first_fit_alloc 2026-06-21 00:56:39 -07:00
nella
601cd7ba5f Add tests. 2026-06-10 11:30:03 +02:00
Mohamed Gaber
e58125b605
Merge remote-tracking branch 'upstream/main' into silimate 2026-06-09 16:22:51 +03:00
Akash Levy
0c3446e8af Fixups for Greptile 2026-06-01 19:03:52 -07:00
Akash Levy
9cc69a3c49 Improvement to opt_balance_tree 2026-06-01 17:56:44 -07:00
Akash Levy
6a8d800e63 Fixes for filtering small cases and catching more larger ones with trickier signatures 2026-05-27 03:40:44 -07:00
Akash Levy
89717069fe Fixup 2026-05-27 01:51:54 -07:00
Akash Levy
e39395132d opt_addcin pass 2026-05-27 00:39:25 -07:00
Akash Levy
2ba8a5cac6 opt parallel prefix and priority encoders 2026-05-20 12:14:50 -07:00
Akash Levy
8485d57841 opt_expr for constant comparisons 2026-04-20 02:03:35 -07:00
Miodrag Milanovic
ced2521b03 Convert gen-tests shell script to python 2026-04-16 11:00:44 +02:00
Robert O'Callahan
7f3b11e56b Add test that connects a wire with init to a constant 2026-03-06 02:20:08 +00:00
Emil J
5f8489d36d
Merge pull request #5666 from YosysHQ/emil/equiv_induct-missing-model-errors
equiv_induct: error on missing model
2026-02-25 15:39:31 +01:00
Akash Levy
5f7658ca7c
Merge branch 'YosysHQ:main' into main 2026-02-05 13:10:34 -08:00
Emil J. Tywoniak
2efd0247a1 opt_hier: fix test 2026-02-03 18:10:29 +01:00
Emil J. Tywoniak
3bfeaee8ca opt_expr: fix const lhs of $pow to $shl 2026-02-03 11:59:00 +01:00
Akash Levy
26f5ff3d74 Merge from upstream 2026-01-26 22:16:11 -08:00
Robert O'Callahan
32e96605d4 Don't update used_signals for retained wires in rmunused_module_signals.
These updates should not be necessary. In fact, if they were necessary, this code
would be buggy, because the results would depend on the order in which wires are traversed:
If wire A is retained, which causes an update to `used_signals`, which then causes wire B
to be retained when it otherwise wouldn't be, then we would get different results depending
on whether A is visited before B.

These updates will also make it difficult to process these wires in parallel.
2026-01-24 03:41:18 +00:00
Akash Levy
b11037e6c6 Merge remote-tracking branch 'upstream/main' 2026-01-21 15:13:57 -08:00
Natalia
d5e1647d11 fix tests with truncation issues 2026-01-14 18:03:30 -08:00
Natalia Kokoromyti
8b6925c5b0 Add opt_balance_tree pass for timing optimization
This pass converts cascaded chains of arithmetic and logic cells ($add,
$mul, $and, $or, $xor) into balanced binary trees to improve timing
performance in hardware synthesis.

The optimization uses a breadth-first search approach to identify chains
of compatible cells, then recursively constructs balanced trees that
reduce the critical path depth.

Features:
- Supports arithmetic cells: $add, $mul
- Supports logic cells: $and, $or, $xor
- Command-line options: -arith (arithmetic only), -logic (logic only)
- Preserves signed/unsigned semantics
- Comprehensive test suite with 30 test cases

Original implementation by Akash Levy <akash@silimate.com> for Silimate.
Upstreamed from https://github.com/Silimate/yosys
2026-01-13 14:20:11 -08:00
Akash Levy
e332ba807d
Merge branch 'YosysHQ:main' into main 2026-01-07 12:40:39 -08:00
Emil J
2e1a2cfacb
Merge pull request #5561 from YosysHQ/emil/opt_expr-test-avoid-multiple-drivers
opt_expr: avoid multiple drivers in test
2026-01-06 14:54:55 +01:00
Akash Levy
1941e8f042 Bump yosys and abc to latest 2025-12-25 03:46:16 -05:00
Emil J. Tywoniak
856d455065 opt_expr: avoid multiple drivers issue #4792 in combined assign tests 2025-12-19 18:32:56 +01:00
Emil J. Tywoniak
772d821fb0 opt_expr: reindent test 2025-12-19 18:32:56 +01:00
N. Engelhardt
45d654e2d7 avoid merging formal properties 2025-12-17 20:25:24 +01:00
Mohamed Gaber
dec28f65ae
Merge remote-tracking branch 'donn/pyosys_bugfixes' into merge_pybind11 2025-10-26 02:39:43 +03:00
Miodrag Milanović
4cdaac003f
Merge pull request #3991 from adrianparvino/alumacc-sign
alumacc: merge independent of sign
2025-10-08 13:02:10 +02:00
Akash Levy
16215b8786 Merge upstream 2025-09-29 20:58:56 -07:00
Martin Povišer
ffe2f7a16d opt_hier: Fix two optimizations conflicting
Fix a conflict between the following two:

 * propagation of tied-together inputs in
 * propagation of unused inputs out
2025-09-29 12:27:27 +02:00
Akash Levy
652a9a63b2 Update to latest and fix all disabled tests 2025-09-28 01:33:08 -07:00
Akash Levy
8204fd1d0b Update Yosys to latest 2025-09-06 16:49:39 -07:00
Emil J. Tywoniak
8333a83cef opt_dff: more explicit testing, typo 2025-08-27 11:29:57 +02:00
Anhijkt
e1276560cd opt_dff: add another test 2025-08-19 23:48:45 +03:00
Anhijkt
e486994f60 opt_dff: add test 2025-08-14 00:13:23 +03:00
Akash Levy
cc733fd11b Merge from upstream 2025-07-30 22:50:14 -07:00
Robert O'Callahan
8b75c06141 Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files. 2025-07-22 10:38:38 +00:00
Akash Levy
3cfbc0d7af
Merge branch 'YosysHQ:main' into main 2025-07-18 09:38:39 -07:00
Martin Povišer
22a44e4333 Start opt_hier 2025-07-05 16:45:52 +02:00
Akash Levy
7e9e4c7afe
Merge branch 'YosysHQ:main' into main 2025-06-23 02:30:24 -07:00