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Code Activity
5236 commits 95 branches 53 tags 45 MiB
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391 commits

Author SHA1 Message Date
Eddie Hung
63eb5cace9 Merge branch 'master' into eddie/muxpack 2019-06-21 11:17:19 -07:00
Clifford Wolf
a8c85d1b4b Update some .gitignore files 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 14:27:57 +02:00
Clifford Wolf
6a6dd5e057 Add proper test for SV-style arrays 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 12:06:07 +02:00
Clifford Wolf
2428fb7dc2 Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into towoe-unpacked_arrays 2019-06-20 12:03:00 +02:00
Clifford Wolf
5a1f1caa44
Merge pull request #1105 from YosysHQ/clifford/fixlogicinit 
Improve handling of initial/default values
 2019-06-19 13:53:07 +02:00
Tobias Wölfel
8b8af10f5e Unpacked array declaration using size 
Allows fixed-sized array dimension specified by a single number.

This commit is based on the work from PeterCrozier
https://github.com/YosysHQ/yosys/pull/560.
But is split out of the original work.
 2019-06-19 12:47:48 +02:00
Clifford Wolf
c330379870 Make tests/aiger less chatty 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 12:20:35 +02:00
Clifford Wolf
fa5fc3f6af Add defvalue test, minor autotest fixes for .sv files 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 12:12:08 +02:00
Eddie Hung
1dd7e23a20 Merge remote-tracking branch 'origin/master' into eddie/muxpack 2019-06-10 10:28:40 -07:00
Eddie Hung
a91ea6612a Add some more comments 2019-06-10 10:27:55 -07:00
Eddie Hung
58f4b106f3 Merge branch 'master' into eddie/muxpack 2019-06-07 15:47:28 -07:00
Eddie Hung
b959bf79c0 Add nonexcl case test, comment out two others 2019-06-07 15:35:15 -07:00
Eddie Hung
1da12c5071 Add @cliffordwolf freduce testcase 2019-06-07 12:12:11 -07:00
Eddie Hung
e263bc249b Add nonexclusive test from @cliffordwolf 2019-06-07 11:54:29 -07:00
Eddie Hung
65924fd12f Test *.aag too, by using *.aig as reference 2019-06-07 11:28:05 -07:00
Eddie Hung
abc40924ed Use ABC to convert from AIGER to Verilog 2019-06-07 11:06:57 -07:00
Eddie Hung
ebe29b6659 Use ABC to convert AIGER to Verilog, then sat against Yosys 2019-06-07 11:05:36 -07:00
Eddie Hung
1b113a0574 Add symbols to AIGER test inputs for ABC 2019-06-07 11:05:25 -07:00
Eddie Hung
0f6e914ef6 Another muxpack test 2019-06-07 08:34:58 -07:00
Clifford Wolf
6d49145497
Merge pull request #1077 from YosysHQ/clifford/pr983 
elaboration system tasks
 2019-06-07 13:39:46 +02:00
Clifford Wolf
f01a61f093 Rename implicit_ports.sv test to implicit_ports.v 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-07 13:12:25 +02:00
Clifford Wolf
a3bbc5365b Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into clifford/pr983 2019-06-07 12:08:42 +02:00
Clifford Wolf
a0b57f2a6f Cleanup tux3-implicit_named_connection 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-07 11:46:16 +02:00
Clifford Wolf
b637b3109d Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys into tux3-implicit_named_connection 2019-06-07 11:41:54 +02:00
Eddie Hung
5c277c6325 Fix and test for balanced case 2019-06-06 14:21:34 -07:00
Eddie Hung
0a66720f6f Fix warnings 2019-06-06 14:01:42 -07:00
Eddie Hung
ccdf989025 Support cascading $pmux.A with $mux.A and $mux.B 2019-06-06 13:51:22 -07:00
Eddie Hung
705388eb24 Add non exclusive test 2019-06-06 12:44:06 -07:00
Eddie Hung
b8620f7b3d One more and tidy up 2019-06-06 12:03:44 -07:00
Eddie Hung
5d4eca5a29 Add a few more special case tests 2019-06-06 11:59:41 -07:00
Eddie Hung
3e76e3a6fa Add tests, fix for != 2019-06-06 11:54:38 -07:00
tux3
88f5977093 SystemVerilog support for implicit named port connections 
This is the `foo foo(.port1, .port2);` SystemVerilog syntax
introduced in IEEE1800-2005.
 2019-06-06 18:07:49 +02:00
Maciej Kurc
b79bd5b3ca Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-04 10:42:42 +02:00
Maciej Kurc
5739cf5265 Added tests for attributes 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-03 09:25:20 +02:00
Clifford Wolf
349c47250a
Merge pull request #1049 from YosysHQ/clifford/fix1047 
Do not use shiftmul peepopt pattern when mul result is truncated
 2019-05-28 19:02:26 +02:00
Clifford Wolf
cb285e4b87 Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-28 17:17:56 +02:00
Clifford Wolf
e3ebac44df Add actual wandwor test that is part of "make test" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-28 16:42:50 +02:00
Stefan Biereigel
816082d5a1
Merge branch 'master' into wandwor 2019-05-27 19:07:46 +02:00
Stefan Biereigel
f68b658b4b reformat wand/wor test 2019-05-27 18:45:54 +02:00
Stefan Biereigel
c5fe04acfd remove port direction workaround from test case 2019-05-27 18:10:39 +02:00
Eddie Hung
f3e86e06e6 Fix init 2019-05-24 18:43:26 -07:00
Eddie Hung
e1cb1bb948 Fix typos 2019-05-24 18:34:27 -07:00
Eddie Hung
d15da4bc11 Add more tests 2019-05-24 18:33:18 -07:00
Eddie Hung
4bd9465ed3 Call proc 2019-05-24 18:32:02 -07:00
Eddie Hung
f0c6b73b72 Fix duplicate driver 2019-05-24 17:44:57 -07:00
Eddie Hung
47f9ea142f Add opt_rmdff tests 2019-05-23 11:26:38 -07:00
Stefan Biereigel
c2caf85f7c add simple test case for wand/wor 2019-05-23 13:57:27 +02:00
Maciej Kurc
1f52332b8d Added tests for Verilog frontent for attributes on parameters and localparams 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-05-16 12:53:43 +02:00
Clifford Wolf
b7ec698d40 Add test case from #997 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-07 19:58:04 +02:00
Clifford Wolf
752553d8e9
Merge pull request #946 from YosysHQ/clifford/specify 
Add specify parser
 2019-05-06 20:57:15 +02:00