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Fix and test for balanced case
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3 changed files with 55 additions and 10 deletions
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@ -110,3 +110,29 @@ always @* begin
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endcase
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end
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endmodule
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module mux_if_bal_8_2 #(parameter N=8, parameter W=2) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
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always @*
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if (s[0] == 1'b0)
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if (s[1] == 1'b0)
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if (s[2] == 1'b0)
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o <= i[0*W+:W];
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else
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o <= i[1*W+:W];
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else
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if (s[2] == 1'b0)
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o <= i[2*W+:W];
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else
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o <= i[3*W+:W];
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else
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if (s[1] == 1'b0)
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if (s[2] == 1'b0)
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o <= i[4*W+:W];
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else
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o <= i[5*W+:W];
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else
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if (s[2] == 1'b0)
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o <= i[6*W+:W];
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else
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o <= i[7*W+:W];
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endmodule
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@ -133,3 +133,18 @@ design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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design -load read
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hierarchy -top mux_if_bal_8_2
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prep
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design -save gold
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muxpack
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opt
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stat
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select -assert-count 7 t:$mux
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select -assert-count 0 t:$pmux
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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