Tobias Wölfel 8b8af10f5e Unpacked array declaration using size ... Allows fixed-sized array dimension specified by a single number. This commit is based on the work from PeterCrozier https://github.com/YosysHQ/yosys/pull/560. But is split out of the original work.		2019-06-19 12:47:48 +02:00
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aiger	Add some more comments	2019-06-10 10:27:55 -07:00
asicworld	Fix FIRRTL to Verilog process instance subfield assignment.	2019-02-25 16:18:13 -08:00
bram
errors	Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,	2018-10-25 02:37:56 +03:00
fsm
hana
liberty	Liberty file parser now accepts superfluous ;	2019-03-27 15:16:19 +01:00
lut	cmp2lut: new techmap pass.	2019-01-02 07:53:31 +00:00
memories	Fix #938 - Crash occurs in case when use write_firrtl command	2019-05-01 13:16:01 -07:00
opt	Fix WREDUCE on FF not fixing ARST_VALUE parameter.	2019-02-22 10:30:42 -08:00
realmath
sat	support repeat loops with constant repeat counts outside of constant functions	2019-04-09 12:28:32 -04:00
share
simple	Rename implicit_ports.sv test to implicit_ports.v	2019-06-07 13:12:25 +02:00
smv
sva	Fix "verific -extnets" for more complex situations	2019-03-26 14:17:46 +01:00
svinterfaces	Fix typo in tests/svinterfaces/runone.sh	2019-05-03 14:40:51 +02:00
techmap
tools	Use ABC to convert from AIGER to Verilog	2019-06-07 11:06:57 -07:00
unit	Build hotfix in tests/unit/Makefile	2016-12-11 10:58:49 +01:00
various	Unpacked array declaration using size	2019-06-19 12:47:48 +02:00
vloghtb