mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-03 21:09:12 +00:00
Code Activity

Cleanup tux3-implicit_named_connection

Browse source 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-06-07 11:46:16 +02:00
parent b637b3109d
commit a0b57f2a6f
3 changed files with 2 additions and 13 deletions
Download patch file Download diff file Expand all files Collapse all files

5
tests/various/implicit_ports.sv → tests/simple/implicit_ports.sv
View file

@ -4,10 +4,8 @@ module alu (input [2:0] a, input [2:0] b, input cin, output cout, output [2:0] r
assign result = a + b;
endmodule
module named_ports(output [2:0] alu_result, output cout);
wire [2:0] a = 3'b010, b = 3'b100;
module named_ports(input [2:0] a, b, output [2:0] alu_result, output cout);
wire cin = 1;
alu alu (
.a(a),
.b, // Implicit connection is equivalent to .b(b)
@ -16,4 +14,3 @@ module named_ports(output [2:0] alu_result, output cout);
.result(alu_result)
);
endmodule

8
tests/various/implicit_ports.ys
View file

@ -1,8 +0,0 @@
read_verilog -sv implicit_ports.sv
proc; opt
flatten
select -module named_ports
sat -verify -prove alu_result 6
sat -verify -set-all-undef cout