1662 commits

Author	SHA1	Message	Date
Eddie Hung	63eb5cace9	Merge branch 'master' into eddie/muxpack	2019-06-21 11:17:19 -07:00
Clifford Wolf	477e566e8d	Fix typo, fixes #1095 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-06-20 15:34:52 +02:00
Clifford Wolf	06eb87bcb7	Improve shregmap help message, fixes #1113 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-06-20 15:23:55 +02:00
Clifford Wolf	11ec7b2aec	Fix typo ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-06-20 12:23:07 +02:00
acw1251	0d888ee7ed	Fixed the help summary line for a few commands	2019-06-19 15:27:04 -04:00
Eddie Hung	96ade54993	Fix bug in #1078, add entry to CHANGELOG	2019-06-19 09:51:11 -07:00
Clifford Wolf	3da5288ce0	Use input default values in hierarchy pass ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-06-19 11:49:20 +02:00
Eddie Hung	5b999ae68d	Elaborate muxpack doc	2019-06-10 10:32:19 -07:00
Eddie Hung	1dd7e23a20	Merge remote-tracking branch 'origin/master' into eddie/muxpack	2019-06-10 10:28:40 -07:00
Eddie Hung	f705f6a0b5	Comment O(N) -> O(N^2)	2019-06-07 15:39:12 -07:00
Eddie Hung	ba52d9b471	Extend ExclusiveDatabase to query SigSpec-s (for $pmux)	2019-06-07 15:34:16 -07:00
Eddie Hung	9b408838f1	Add ExclusiveDatabase to check exclusive $eq/$logic_not cell results	2019-06-07 14:18:17 -07:00
Eddie Hung	887df8914c	Resolve @cliffordwolf comment on redundant check	2019-06-07 11:37:52 -07:00
Eddie Hung	5ab59cd59e	Resolve @cliffordwolf comment on sigmap	2019-06-07 11:36:19 -07:00
Eddie Hung	30abdaf3b2	Allow muxcover costs to be changed	2019-06-07 08:34:11 -07:00
Eddie Hung	5c277c6325	Fix and test for balanced case	2019-06-06 14:21:34 -07:00
Eddie Hung	ccdf989025	Support cascading $pmux.A with $mux.A and $mux.B	2019-06-06 13:51:22 -07:00
Eddie Hung	dc7b8c4b94	More cleanup	2019-06-06 12:56:34 -07:00
Eddie Hung	978fda94f6	Fix spacing	2019-06-06 12:46:42 -07:00
Eddie Hung	d2172c6846	Non chain user check using next_sig	2019-06-06 12:44:50 -07:00
Eddie Hung	83450a9489	Move muxpack from passes/techmap to passes/opt	2019-06-06 12:15:13 -07:00
Eddie Hung	3dd0682f29	Update doc	2019-06-06 12:11:59 -07:00
Eddie Hung	3e76e3a6fa	Add tests, fix for !=	2019-06-06 11:54:38 -07:00
Eddie Hung	543dd11c7e	Missing file	2019-06-06 11:03:45 -07:00
Eddie Hung	7bd1c664a6	Initial adaptation of muxpack from shregmap	2019-06-06 10:51:02 -07:00
Clifford Wolf	e4e1cd6930	Merge pull request #1071 from YosysHQ/eddie/fix_1070 ... Fix typo in opt_rmdff causing register to be incorrectly removed	2019-06-06 06:50:12 +02:00
Clifford Wolf	50e2dce5e7	Merge pull request #1072 from YosysHQ/eddie/fix_1069 ... Error out if no top module given before 'sim'	2019-06-06 06:49:07 +02:00
Eddie Hung	fd8ef128bf	Missing doc for -tech xilinx in shregmap	2019-06-05 14:21:44 -07:00
Eddie Hung	dd134914cc	Error out if no top module given before 'sim'	2019-06-05 14:16:24 -07:00
Eddie Hung	feb2ddb52b	Fix typo in opt_rmdff	2019-06-05 14:08:14 -07:00
Eddie Hung	a3a80b755c	Merge pull request #1067 from YosysHQ/clifford/fix1065 ... Suppress driver-driver conflict warning for unknown cell types	2019-06-05 09:59:05 -07:00
Clifford Wolf	b33176dafb	Major rewrite of wire selection in setundef -init ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-06-05 10:26:48 +02:00
Clifford Wolf	6cc60ffd67	Indent fix ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-06-05 09:53:06 +02:00
Clifford Wolf	00d32eb73d	Merge pull request #999 from jakobwenzel/setundefInitFix ... initialize more registers in setundef -init	2019-06-05 09:50:15 +02:00
Clifford Wolf	4190d7c094	Fix typo in fmcombine log message, fixes #1063 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-06-05 09:26:44 +02:00
Clifford Wolf	8a6f9977f6	Suppress driver-driver conflict warning for unknown cell types, fixes #1065 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-06-05 09:14:12 +02:00
Clifford Wolf	90ec2cda42	Fix "tee" handling of log_streams ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-05-31 09:28:51 +02:00
Clifford Wolf	349c47250a	Merge pull request #1049 from YosysHQ/clifford/fix1047 ... Do not use shiftmul peepopt pattern when mul result is truncated	2019-05-28 19:02:26 +02:00
Clifford Wolf	cb285e4b87	Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-05-28 17:17:56 +02:00
Clifford Wolf	ba2185ead8	Refactor hierarchy wand/wor handling ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-05-28 16:43:25 +02:00
Stefan Biereigel	816082d5a1	Merge branch 'master' into wandwor	2019-05-27 19:07:46 +02:00
Stefan Biereigel	ed625a3102	move wand/wor resolution into hierarchy pass	2019-05-27 18:00:22 +02:00
Clifford Wolf	2a9c68e2d6	Merge pull request #1026 from YosysHQ/clifford/fix1023 ... Keep zero-width wires in opt_clean if and only if they are ports	2019-05-27 13:24:19 +02:00
Eddie Hung	d4fb6cac7c	Revert enable check	2019-05-25 12:55:57 -07:00
Eddie Hung	822d0b7789	opt_rmdff to optimise even in presence of enable signal, even removing	2019-05-24 18:30:51 -07:00
Eddie Hung	0d66103cbb	Add comments	2019-05-24 16:33:10 -07:00
Eddie Hung	357b1de6bc	Resolve @cliffordwolf review, set even if !has_init	2019-05-24 16:15:22 -07:00
Eddie Hung	5ac7e38d0a	Fix spacing	2019-05-23 12:58:30 -07:00
Eddie Hung	50ed34a6d0	opt_rmdff to work on $dffe and $_DFFE_*	2019-05-23 11:26:18 -07:00
Clifford Wolf	e3f9ccf56d	Keep zero-width wires in opt_clean if and only if they are ports, fixes #1023 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-05-22 13:57:36 +02:00