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yosys/passes
Clifford Wolf 6cc60ffd67 Indent fix
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-05 09:53:06 +02:00
..
cmds Indent fix 2019-06-05 09:53:06 +02:00
equiv Add -undef option to equiv_opt, passed to equiv_induct 2019-04-26 11:16:48 -07:00
fsm fsm_opt: Fix runtime error for FSMs without a reset state 2019-02-07 10:35:36 +00:00
hierarchy Refactor hierarchy wand/wor handling 2019-05-28 16:43:25 +02:00
memory memory_bram: Fix multiport make_transp 2019-04-07 16:56:31 +01:00
opt Merge pull request #1026 from YosysHQ/clifford/fix1023 2019-05-27 13:24:19 +02:00
pmgen Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047 2019-05-28 17:17:56 +02:00
proc Improve proc full_case detection and handling, fixes #931 2019-04-18 15:13:47 +02:00
sat Fix typo in fmcombine log message, fixes #1063 2019-06-05 09:26:44 +02:00
techmap Fix two instances of integer-assignment to string. 2019-05-14 22:01:15 -07:00
tests flowmap: implement depth relaxation. 2019-01-08 01:13:05 +00:00