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https://github.com/YosysHQ/yosys
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Support cascading $pmux.A with $mux.A and $mux.B
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parent
dc7b8c4b94
commit
ccdf989025
3 changed files with 65 additions and 17 deletions
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@ -51,10 +51,12 @@ struct MuxpackWorker
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for (auto cell : module->cells())
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{
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if (cell->type.in("$mux") && !cell->get_bool_attribute("\\keep"))
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if (cell->type.in("$mux", "$pmux") && !cell->get_bool_attribute("\\keep"))
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{
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SigSpec a_sig = sigmap(cell->getPort("\\A"));
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SigSpec b_sig = sigmap(cell->getPort("\\B"));
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SigSpec b_sig;
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if (cell->type == "$mux")
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b_sig = sigmap(cell->getPort("\\B"));
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SigSpec y_sig = sigmap(cell->getPort("\\Y"));
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if (sig_chain_next.count(a_sig))
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@ -65,12 +67,14 @@ struct MuxpackWorker
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candidate_cells.insert(cell);
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}
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if (sig_chain_next.count(b_sig))
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for (auto b_bit : b_sig.bits())
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sigbit_with_non_chain_users.insert(b_bit);
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else {
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sig_chain_next[b_sig] = cell;
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candidate_cells.insert(cell);
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if (!b_sig.empty()) {
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if (sig_chain_next.count(b_sig))
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for (auto b_bit : b_sig.bits())
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sigbit_with_non_chain_users.insert(b_bit);
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else {
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sig_chain_next[b_sig] = cell;
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candidate_cells.insert(cell);
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}
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}
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sig_chain_prev[y_sig] = cell;
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@ -88,10 +92,16 @@ struct MuxpackWorker
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{
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for (auto cell : candidate_cells)
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{
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log_debug("Considering %s (%s)\n", log_id(cell), log_id(cell->type));
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SigSpec next_sig = cell->getPort("\\A");
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if (sig_chain_prev.count(next_sig) == 0) {
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next_sig = cell->getPort("\\B");
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if (sig_chain_prev.count(next_sig) == 0)
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if (cell->type == "$mux") {
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next_sig = cell->getPort("\\B");
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if (sig_chain_prev.count(next_sig) == 0)
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goto start_cell;
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}
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else
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goto start_cell;
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}
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@ -103,10 +113,7 @@ struct MuxpackWorker
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Cell *c1 = sig_chain_prev.at(next_sig);
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Cell *c2 = cell;
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if (c1->type != c2->type)
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goto start_cell;
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if (c1->parameters != c2->parameters)
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if (c1->getParam("\\WIDTH") != c2->getParam("\\WIDTH"))
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goto start_cell;
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}
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@ -220,15 +227,16 @@ struct MuxpackWorker
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};
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struct MuxpackPass : public Pass {
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MuxpackPass() : Pass("muxpack", "$mux cell cascades to $pmux") { }
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MuxpackPass() : Pass("muxpack", "$mux/$pmux cascades to $pmux") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" muxpack [selection]\n");
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log("\n");
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log("This pass converts cascaded chains of $mux cells (e.g. those created by if-else\n");
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log("constructs) into $pmux cells.\n");
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log("This pass converts cascaded chains of $pmux cells (e.g. those create from case\n");
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log("constructs) and $mux cells (e.g. those created by if-else constructs) into \n");
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log("into $pmux cells.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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