Eddie Hung dd134914cc Error out if no top module given before 'sim'		2019-06-05 14:16:24 -07:00
..
cmds	Major rewrite of wire selection in setundef -init	2019-06-05 10:26:48 +02:00
equiv	Add -undef option to equiv_opt, passed to equiv_induct	2019-04-26 11:16:48 -07:00
fsm	fsm_opt: Fix runtime error for FSMs without a reset state	2019-02-07 10:35:36 +00:00
hierarchy	Refactor hierarchy wand/wor handling	2019-05-28 16:43:25 +02:00
memory	memory_bram: Fix multiport make_transp	2019-04-07 16:56:31 +01:00
opt	Suppress driver-driver conflict warning for unknown cell types, fixes #1065	2019-06-05 09:14:12 +02:00
pmgen	Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047	2019-05-28 17:17:56 +02:00
proc	Improve proc full_case detection and handling, fixes #931	2019-04-18 15:13:47 +02:00
sat	Error out if no top module given before 'sim'	2019-06-05 14:16:24 -07:00
techmap	Fix two instances of integer-assignment to string.	2019-05-14 22:01:15 -07:00
tests	flowmap: implement depth relaxation.	2019-01-08 01:13:05 +00:00