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150 commits

Author SHA1 Message Date
Emil J. Tywoniak
58f95dbab8 proc_dff: better error context
(cherry picked from commit 404ce980e4)
2026-06-24 16:48:01 +02:00
Emil J. Tywoniak
0e30f20be3 proc_mux: include switch expression location in $eq src
(cherry picked from commit 383daa1eb3)
2026-06-24 16:45:56 +02:00
Emil J. Tywoniak
a6992682bf proc_mux, genrtlil: make use of case_src for better case condition vs block tracking
(cherry picked from commit a24c260998)
2026-06-24 16:39:47 +02:00
Emil J. Tywoniak
55633b1e85 proc_mux: copy switch src to _CMP wire
(cherry picked from commit 502ba3734b)
2026-06-24 16:32:05 +02:00
Emil J. Tywoniak
0d3c218d6b proc_mux: copy mux src to Y port
(cherry picked from commit da65a18f39)
2026-06-24 16:31:20 +02:00
Emil J. Tywoniak
bcf3af0a21 proc_mux: add comments
(cherry picked from commit ee800087e8)
2026-06-24 16:29:58 +02:00
Emil J. Tywoniak
e5ef56f1e8 proc_mux: optimize source map locality for index density
(cherry picked from commit b3aea1b5d2)
2026-06-24 16:28:16 +02:00
Emil J. Tywoniak
6bd2609f34 proc_dff: add wire src attributes to dff cells
(cherry picked from commit 4072bcfd0b)
2026-06-24 16:26:55 +02:00
Emil J. Tywoniak
bf0a3b1e72 proc_mux: default to case src when action src is missing
(cherry picked from commit 469083dcaa)
2026-06-24 16:21:26 +02:00
Emil J. Tywoniak
451b1c074c proc_mux: refactor
(cherry picked from commit 778a667a91)
2026-06-24 16:18:04 +02:00
Emil J. Tywoniak
83a15e0038 proc_mux: emit fused action location src attributes on procmuxes
(cherry picked from commit cacd584347)
2026-06-24 15:29:08 +02:00
Emil J. Tywoniak
6646b1dbf9 rtlil: add source tracking to CaseRule actions
(cherry picked from commit c36370f227)
2026-06-24 15:23:12 +02:00
Emil J. Tywoniak
2330860c48 rtlil: replace SigSig actions with new type SyncAction
(cherry picked from commit 94a53e08bc)
2026-06-24 15:14:53 +02:00
Emil J. Tywoniak
0c450ce8c8 WIP migration to twine 2026-06-18 19:27:41 +02:00
Emil J. Tywoniak
3a5f5c77bf twine: avoid TwinePool::lookup 2026-06-16 22:57:13 +02:00
Emil J. Tywoniak
d22805bd47 WIP 2026-06-12 16:25:07 +02:00
Emil J. Tywoniak
c3ffbf6fae WIP 2026-06-12 00:18:53 +02:00
Emil J. Tywoniak
afdae7b87e WIP 2026-06-11 20:02:02 +02:00
Emil J. Tywoniak
8e522b08c0 WIP 2026-06-11 13:17:54 +02:00
Emil J. Tywoniak
f592f2f3af WIP 2026-06-10 19:22:53 +02:00
Emil J. Tywoniak
ca632e82c4 rtlil: set Module* on inner-process AttrObjects at construction 2026-06-10 14:54:12 +02:00
Emil J. Tywoniak
f1edb571f2 rtlil: evacuate src_id_ from AttrObject to per-Design meta vector 2026-06-10 14:54:05 +02:00
Emil J. Tywoniak
3424c00cd0 twine 2026-06-10 14:53:45 +02:00
Codexplorer
e41b969da2 Refactored uses of log_id() 2026-05-08 20:59:24 -07:00
Krystine Sherwin
c0e29ef57c
proc_clean: Removing an empty full_case is doing something 2026-01-07 13:10:32 +13:00
Robert O'Callahan
2d5ce8c363 Update passes/proc to avoid bits() 2025-09-16 03:17:23 +00:00
Robert O'Callahan
e0ae7b7af4 Remove .c_str() calls from log()/log_error()
There are some leftovers, but this is an easy regex-based approach that removes most of them.
2025-09-11 20:59:37 +00:00
Robert O'Callahan
c7df6954b9 Remove .c_str() from stringf parameters 2025-09-01 23:34:42 +00:00
Krystine Sherwin
ab0e3cc05f
Proc: Use selections consistently
All `proc_*` passes now use the same module and process for loops, using `design->all_selected_modules()` and `mod->selected_processes()` respectively.
This simplifies the code, and makes the couple `proc_*` passes that were ignoring boxed modules stop doing that (which seems to have been erroneous rather than intentional).
2025-05-31 12:04:42 +12:00
Emil J. Tywoniak
a58481e9b7 mark all hash_into methods nodiscard 2025-01-14 12:39:15 +01:00
Emil J. Tywoniak
b9b9515bb0 hashlib: hash_eat -> hash_into 2024-12-18 15:09:25 +01:00
Emil J. Tywoniak
4e29ec1854 hashlib: acc -> eat 2024-12-18 15:09:25 +01:00
Emil J. Tywoniak
d071489ab1 hashlib: redo interface for flexibility 2024-12-18 14:49:25 +01:00
George Rennie
626dbbe1e0 proc_dff: fix early return bug
* early return caused proc_dff to stop considering rules after seeing
  one async rule - this is because continue should have been used to
  continue to procecssing the next rule instead of returning from the
  function
2024-11-07 00:06:03 +01:00
Emil J. Tywoniak
785bd44da7 rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
George Rennie
bdb5d45591 proc_dff: respect sync rule priorities when generating complex dffsrs
* This fixes #4560, where previously the order that sync rules were
  processed in depended on the order they were pulled out of a std::map.
  This PR changes this to process them in the order they are found in,
  respecting the priorities among the async signals
2024-08-28 15:48:07 +01:00
Martin Povišer
7ee685a0b0 proc_rom: Set src on the emitted memory 2024-07-25 23:14:27 +01:00
Martin Povišer
db947e4c71
Merge pull request #4218 from kivikakk/proc_rom-actionless-switch
proc_rom: don't assert on big actionless switch.
2024-02-19 16:21:40 +01:00
Amelia Cuss
bf4a46ccb3 proc_rom: don't assert on big actionless switch.
See the test case.  PROC_ROM will consider this for evaluation, even
though -- without any actions -- lhs is empty (but still "uniform").
A zero-width memory is constructed, which later fails check with:

ERROR: Assert `width != 0' failed in kernel/mem.cc:518.

Ensure we don't proceed if there's nothing to encode.
2024-02-18 01:33:28 +11:00
Martin Povišer
862f2fd705 proc_dlatch: Include $bwmux among considered mux cells 2024-02-08 00:08:50 +01:00
Charlotte
860e3e4056 proc_clean: only consider fully-defined switch operands too. 2023-08-12 02:46:31 +02:00
Charlotte
bf84861fc2 proc_clean: only consider fully-defined case operands. 2023-08-12 02:46:31 +02:00
Charlotte
63e4114233 proc_prune: avoid using invalidated iterator
An `std::vector<T>::reverse_iterator` stores the
`std::vector<T>::iterator` which points to the (forwards-ordered)
*following* item.  Thus while `vec.rbegin()` dereferences to the final
item of `vec`, the iterator it wraps (`vec.rbegin().base()`) is equal to
`vec.end()`.

In the remove case here, we advance `it` (backwards), erasing the item
we just advanced past by grabbing its (pre-increment) base
forward-iterator and subtracting 1.

The iterator maths here is obviously all OK, but the forward-iterator
that `it` wraps post-increment actually points to the item we just
removed.  That iterator was invalidated by the `erase()` call.

That this works anyway is (AFAICT) some combination of luck and/or
promises that aren't part of the C++ spec, but MSVC's debug iterator
support picks this up.

`erase()` returns the new iterator that follows the item just erased,
which happens to be the exact one we want our reverse-iterator to wrap
for the next loop; we get a fresh iterator to the same base, now without
the preceding item.
2023-06-21 19:53:08 +10:00
Miodrag Milanovic
6574553189 Fixes for some of clang scan-build detected issues 2023-01-17 12:58:08 +01:00
Marcelina Kościelnicka
9450f308f0 proc_rom: Add special handling of const-0 address bits. 2022-05-18 17:32:30 +02:00
Marcelina Kościelnicka
990c9b8e11 Add proc_rom pass. 2022-05-13 00:37:14 +02:00
Marcelina Kościelnicka
8d881826eb proc_dff: Emit $aldff. 2021-10-27 14:14:24 +02:00
Marcelina Kościelnicka
faacc7ad89 proc_prune: Make assign removal and promotion per-bit, remember promoted bits.
Fixes #2962.
2021-08-14 15:26:11 +02:00
Marcelina Kościelnicka
24027b5446 proc_memwr: Use the v2 memwr cell. 2021-08-11 13:34:10 +02:00
Zachary Snow
c016f6a423 proc_rmdead: use explicit pattern set when there are no wildcards
If width of a case expression was large, explicit patterns could cause
the existing logic to take an extremely long time, or exhaust the
maximum size of the underlying set. For cases where all of the patterns
are fully defined and there are no constants in the case expression,
this change uses a simple set to track which patterns have been seen.
2021-07-29 20:55:59 -04:00