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yosys/passes/proc
2026-06-24 16:28:16 +02:00
..
Makefile.inc Add proc_rom pass. 2022-05-13 00:37:14 +02:00
proc.cc Add proc_rom pass. 2022-05-13 00:37:14 +02:00
proc_arst.cc rtlil: add source tracking to CaseRule actions 2026-06-24 15:23:12 +02:00
proc_clean.cc rtlil: replace SigSig actions with new type SyncAction 2026-06-24 15:14:53 +02:00
proc_dff.cc proc_dff: add wire src attributes to dff cells 2026-06-24 16:26:55 +02:00
proc_dlatch.cc rtlil: replace SigSig actions with new type SyncAction 2026-06-24 15:14:53 +02:00
proc_init.cc rtlil: replace SigSig actions with new type SyncAction 2026-06-24 15:14:53 +02:00
proc_memwr.cc WIP 2026-06-12 00:18:53 +02:00
proc_mux.cc proc_mux: optimize source map locality for index density 2026-06-24 16:28:16 +02:00
proc_prune.cc rtlil: replace SigSig actions with new type SyncAction 2026-06-24 15:14:53 +02:00
proc_rmdead.cc WIP migration to twine 2026-06-18 19:27:41 +02:00
proc_rom.cc rtlil: add source tracking to CaseRule actions 2026-06-24 15:23:12 +02:00