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proc_dff: add wire src attributes to dff cells

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(cherry picked from commit 4072bcfd0b)
This commit is contained in:
Emil J. Tywoniak 2025-11-07 21:32:09 +01:00
parent 88865ef7ab
commit 6bd2609f34
2 changed files with 27 additions and 5 deletions
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25
passes/proc/proc_dff.cc
View file

@ -53,6 +53,25 @@ RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc)
return lvalue;
}
void transfer_wire_sources(const SigSpec& sig, Cell* cell)
{
std::vector<TwineRef> refs;
pool<TwineRef> seen;
TwineRef existing = cell->src_id();
if (existing != Twine::Null) {
refs.push_back(existing);
seen.insert(existing);
}
for (auto chunk : sig.chunks())
if (chunk.wire) {
TwineRef s = chunk.wire->src_id();
if (s != Twine::Null && seen.insert(s).second)
refs.push_back(s);
}
if (!refs.empty())
cell->set_src_attribute(cell->module->design->twines.concat(std::span<const TwineRef>{refs}));
}
void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, RTLIL::SigSpec clk, bool clk_polarity,
std::vector<std::pair<RTLIL::SigSpec, RTLIL::SyncRule*>> &async_rules, RTLIL::Process *proc)
{
@ -83,6 +102,8 @@ void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec
RTLIL::Cell *cell = mod->addDffsr(Twine{sstr.str()}, clk, sig_sr_set, sig_sr_clr, sig_d, sig_q, clk_polarity);
cell->attributes = proc->attributes;
transfer_wire_sources(sig_q, cell);
cell->module->design->merge_src(cell, proc);
log(" created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n",
log_id(cell->type), log_id(cell), clk_polarity ? "positive" : "negative");
@ -96,6 +117,8 @@ void gen_aldff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec sig_set
RTLIL::Cell *cell = mod->addCell(mod->design->twines.add(std::string{sstr.str()}), TW($aldff));
cell->attributes = proc->attributes;
transfer_wire_sources(sig_out, cell);
cell->module->design->merge_src(cell, proc);
cell->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size());
cell->parameters[ID::ALOAD_POLARITY] = RTLIL::Const(set_polarity, 1);
@ -118,6 +141,8 @@ void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_rst, RT
RTLIL::Cell *cell = mod->addCell(mod->design->twines.add(std::string{sstr.str()}), clk.empty() ? TW($ff) : arst ? TW($adff) : TW($dff));
cell->attributes = proc->attributes;
transfer_wire_sources(sig_out, cell);
cell->module->design->merge_src(cell, proc);
cell->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size());
if (arst) {

7
tests/proc/proc_mux_src.ys
View file

@ -5,9 +5,9 @@ check -assert
select -assert-count 2 tiny2/t:$eq
select -assert-count 1 tiny2/t:$eq a:src=proc_mux_src.v:81.4-81.10 %i
select -assert-count 1 tiny2/t:$eq a:src=proc_mux_src.v:84.4-84.10 %i
# Flops cover the whole process
# Flops cover the assigned to wire and whole process
select -assert-count 1 tiny2/t:$dff
select -assert-count 1 tiny2/t:$dff a:src=proc_mux_src.v:78.2-91.5 %i
select -assert-count 1 tiny2/t:$dff a:src=proc_mux_src.v:76.19-76.22|proc_mux_src.v:78.2-91.5
# Muxes are marked to the exact assignment statements they represent including the explicit default case
select -assert-count 1 tiny2/t:$pmux
select -assert-count 1 tiny2/t:$pmux a:src=proc_mux_src.v:80.5-80.13|proc_mux_src.v:83.5-83.15|proc_mux_src.v:86.5-86.15
@ -18,8 +18,6 @@ select -assert-count 1 tiny/t:$mux
select -assert-count 1 tiny/t:$mux a:proc_mux_src.v:65.5-65.13|proc_mux_src.v:63.3-67.10
select -assert-count 0 tiny/t:$reduce_or
dump nested
#dump nested/t:$pmux
# $reduce_or src covers the entire list of comparison RHSs
# Each snippet is treated separately so it gets its own $eq and $reduce_or etc
select -assert-count 3 nested/t:$reduce_or
@ -30,4 +28,3 @@ select -assert-count 5 nested/t:$pmux
select -assert-count 1 nested/t:$pmux a:src=proc_mux_src.v:21.5-21.20|proc_mux_src.v:26.5-26.20|proc_mux_src.v:32.5-45.12|proc_mux_src.v:48.5-48.19 %i
# No nesting for output reg arith
select -assert-count 1 nested/t:$pmux a:src=proc_mux_src.v:23.5-23.18|proc_mux_src.v:28.5-28.18|proc_mux_src.v:31.5-31.18|proc_mux_src.v:50.5-50.18 %i
dump nested/t:$pmux