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Code Activity
4622 commits 122 branches 59 tags 73 MiB
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620 commits

Author SHA1 Message Date
Keith Rothman
5e0339855f Add additional cells sim models for core 7-series primatives. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-04-09 09:01:53 -07:00
David Shah
46f6a60d58 xilinx: Add keep attribute where appropriate 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 13:57:17 +00:00
Clifford Wolf
fe1fb1336b Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-19 20:30:28 +01:00
Clifford Wolf
9284cf92b8 Remove ice40/cells_sim.v hack to avoid warning for blocking memory writes 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-12 20:14:18 +01:00
Clifford Wolf
ff4c2a14ae Fix typo in ice40_braminit help msg 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-09 13:24:55 -08:00
Clifford Wolf
2ace1b0041
Merge pull request #859 from smunaut/ice40_braminit 
iCE40 BRAM primitives init from file
 2019-03-09 13:24:10 -08:00
Sylvain Munaut
5b6f591033 ice40: Run ice40_braminit pass by default 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-03-08 00:15:46 +01:00
Sylvain Munaut
e71055cfe8 ice40: Add ice40_braminit pass to allow initialization of BRAM from file 
This adds a INIT_FILE attribute to the SB_RAM40_4K blocks that will
initialize content from a hex file. Same behavior is imlemented in the
simulation model and in a new pass for actual synthesis

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-03-08 00:15:46 +01:00
Clifford Wolf
350dfd3745 Add link to SF2 / igloo2 macro library guide 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-07 09:08:26 -08:00
Clifford Wolf
8b0719d1e3 Improvements in sf2 cells_sim.v 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-06 16:18:49 -08:00
Clifford Wolf
2d2c1617ee Add sf2 techmap rules for more FF types 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-06 15:47:54 -08:00
Clifford Wolf
78762316aa Refactor SF2 iobuf insertion, Add clkint insertion 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-06 00:41:02 -08:00
Clifford Wolf
da5181a3df Improvements in SF2 flow and demo 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-05 20:36:00 -08:00
Clifford Wolf
bfcd46dbd3
Merge pull request #842 from litghost/merge_upstream 
Changes required for VPR place and route in synth_xilinx
 2019-03-05 15:33:19 -08:00
Clifford Wolf
724576a4e2
Merge pull request #850 from daveshah1/ecp5_warn_conflict 
ecp5: Demote conflicting FF init values to a warning
 2019-03-05 15:23:01 -08:00
Clifford Wolf
13844c7658 Use "write_edif -pvector bra" for Xilinx EDIF files 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-05 15:16:13 -08:00
Keith Rothman
228f132ec3 Revert BRAM WRITE_MODE changes. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-04 09:22:22 -08:00
David Shah
777864d02e ecp5: Demote conflicting FF init values to a warning 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-04 11:26:20 +00:00
Keith Rothman
3e16f75bc6 Revert FF models to include IS_x_INVERTED parameters. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-01 14:41:21 -08:00
Keith Rothman
5ebeca12eb Use singular for disabling of DRAM or BRAM inference. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-01 14:35:14 -08:00
Keith Rothman
eccaf101d8 Modify arguments to match existing style. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-01 12:14:27 -08:00
Keith Rothman
3090951d54 Changes required for VPR place and route synth_xilinx. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-01 12:02:27 -08:00
Miodrag Milanovic
ca2b3feed8 Fix ECP5 cells_sim for iverilog 2019-03-01 19:25:23 +01:00
Clifford Wolf
a82a7eb42e
Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode 
ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
 2019-02-28 20:27:27 -08:00
Elms
cd2902ab1f ice40: use 2 bits for READ/WRITE MODE for SB_RAM map 
EBLIF output .param will only use necessary 2 bits

Signed-off-by: Elms <elms@freshred.net>
 2019-02-28 16:23:40 -08:00
Larry Doolittle
e2fc18f27b Reduce amount of trailing whitespace in code base 2019-02-28 14:58:11 -08:00
Clifford Wolf
41e5028f98
Merge pull request #794 from daveshah1/ecp5improve 
ECP5 Improvements
 2019-02-28 14:46:56 -08:00
Larry Doolittle
7a40294e93 techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module 2019-02-26 09:40:46 -08:00
Larry Doolittle
61fc411c5d Clean up some whitepsace outliers 2019-02-26 09:39:46 -08:00
David Shah
fa2f595cfa ecp5: Compatibility with Migen AsyncResetSynchronizer 
Signed-off-by: David Shah <davey1576@gmail.com>
 2019-02-25 13:24:30 +00:00
Clifford Wolf
344afdcd5f
Merge pull request #740 from daveshah1/improve_dress 
Improve ABC netname preservation
 2019-02-22 01:16:34 +01:00
Clifford Wolf
2fe1c830eb Bugfix in ice40_dsp 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-21 13:28:46 +01:00
Clifford Wolf
84999a7e68 Add ice40 test_dsp_map test case generator 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-20 17:18:59 +01:00
Clifford Wolf
218e9051bb Add "synth_ice40 -dsp" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-20 16:42:27 +01:00
Clifford Wolf
7bf4e4a185 Improve iCE40 SB_MAC16 model 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-20 12:55:20 +01:00
David Shah
bb56cb738d ecp5: Add DDRDLLA 
Signed-off-by: David Shah <davey1576@gmail.com>
 2019-02-19 19:34:37 +00:00
David Shah
c36f15b489 ecp5: Add DELAYF/DELAYG blackboxes 
Signed-off-by: David Shah <davey1576@gmail.com>
 2019-02-19 14:10:43 +00:00
Clifford Wolf
62493c91b2 Add first draft of functional SB_MAC16 model 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-19 14:47:27 +01:00
David Shah
e0bc190879 ecp5: Add ECLKSYNCB blackbox 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-13 11:23:25 +00:00
David Shah
7913baedd8 ecp5: Full set of IO-related blackboxes 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-12 12:04:41 +00:00
David Shah
95789c6136 ecp5: Use abc -dress 
Signed-off-by: David Shah <davey1576@gmail.com>
 2019-02-06 22:23:13 +01:00
David Shah
7ef2333497 ice40: Use abc -dress in synth_ice40 
Signed-off-by: David Shah <davey1576@gmail.com>
 2019-02-06 22:23:13 +01:00
Miodrag Milanovic
0de328da8f Fixed Anlogic simulation model 2019-01-25 19:25:25 +01:00
David Shah
549b8e74b2 ecp5: Support for flipflop initialisation 
Signed-off-by: David Shah <dave@ds0.me>
 2019-01-22 16:02:56 +00:00
David Shah
ee8c9e854f ecp5: Add LSRMODE to flipflops for PRLD support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-01-21 12:35:22 +00:00
David Shah
d8003e87d1 ecp5: More blackboxes 
Signed-off-by: David Shah <dave@ds0.me>
 2019-01-21 12:34:34 +00:00
David Shah
01ea72f53a ecp5: Increase threshold for ALU mapping 
Signed-off-by: David Shah <dave@ds0.me>
 2019-01-21 12:33:47 +00:00
Clifford Wolf
db5765b443 Add SF2 IO buffer insertion 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-17 14:38:37 +01:00
Clifford Wolf
841ca74c90 Add "synth_sf2 -vlog", fix "synth_sf2 -edif" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-17 13:33:45 +01:00
Clifford Wolf
e041ae3c6d
Merge pull request #777 from mmicko/achronix_cell_sim_fix 
Fix cells_sim.v for Achronix FPGA
 2019-01-04 15:18:18 +01:00