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yosys/techlibs
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Sylvain Munaut e71055cfe8 ice40: Add ice40_braminit pass to allow initialization of BRAM from file 
This adds a INIT_FILE attribute to the SB_RAM40_4K blocks that will
initialize content from a hex file. Same behavior is imlemented in the
simulation model and in a new pass for actual synthesis

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-03-08 00:15:46 +01:00
..
achronix Merge pull request #777 from mmicko/achronix_cell_sim_fix 2019-01-04 15:18:18 +01:00
anlogic Fixed Anlogic simulation model 2019-01-25 19:25:25 +01:00
common Merge pull request #772 from whitequark/synth_lut 2019-01-02 15:44:57 +01:00
coolrunner2 Unify usage of noflatten among architectures 2019-01-04 11:37:25 +01:00
easic Fix typographical and grammatical errors and inconsistencies. 2019-01-02 13:12:17 +00:00
ecp5 Clean up some whitepsace outliers 2019-02-26 09:39:46 -08:00
gowin Unify usage of noflatten among architectures 2019-01-04 11:37:25 +01:00
greenpak4 techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module 2019-02-26 09:40:46 -08:00
ice40 ice40: Add ice40_braminit pass to allow initialization of BRAM from file 2019-03-08 00:15:46 +01:00
intel Unify usage of noflatten among architectures 2019-01-04 11:37:25 +01:00
sf2 Add SF2 IO buffer insertion 2019-01-17 14:38:37 +01:00
xilinx Fix typographical and grammatical errors and inconsistencies. 2019-01-02 13:12:17 +00:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00