586 commits

Author	SHA1	Message	Date
Clifford Wolf	5dab327b30	More fixes in ast expression sign/width handling	2013-07-09 23:41:43 +02:00
Clifford Wolf	00a6c1d9a5	Major redesign of expr width/sign detecion (verilog/ast frontend)	2013-07-09 14:31:57 +02:00
Clifford Wolf	e8da3ea7b6	Fixed another bug found using vloghammer	2013-07-07 16:49:30 +02:00
Clifford Wolf	eff68560a2	Fixed AST_CONSTANT node generation	2013-07-07 15:40:26 +02:00
Clifford Wolf	56432a920f	Added defparam support to Verilog/AST frontend	2013-07-04 14:12:33 +02:00
Clifford Wolf	0c6ffc4c65	More fixes for bugs found using xsthammer	2013-06-13 11:18:45 +02:00
Clifford Wolf	4b311b7b99	Further improved and extended xsthammer	2013-06-11 19:49:35 +02:00
Clifford Wolf	a5c30183b5	Sign-extension related fixes in SatGen and AST frontend	2013-06-10 17:10:06 +02:00
Clifford Wolf	59dd02baa2	Fixes and improvements in AST const folding	2013-06-10 13:56:03 +02:00
Clifford Wolf	db98a18edb	Enabled AST/Verilog front-end optimizations per default	2013-06-10 13:19:04 +02:00
Clifford Wolf	46fbe9d262	Added SAT generator and simple sat_solve command	2013-06-07 13:59:13 +02:00
Clifford Wolf	ed0e2f7a6f	Added log_assert() api	2013-05-24 14:38:36 +02:00
Clifford Wolf	375f83c5ec	Fixed memory leak in ilang frontend	2013-05-23 12:55:59 +02:00
Johann Glaser	10a195c0a1	added option '-Dname[=definition]' to command 'read_verilog'	2013-05-19 17:07:52 +02:00
Clifford Wolf	c5ee2b306a	Merge branch 'bugfix'	2013-05-16 16:44:45 +02:00
Clifford Wolf	6cc8e848b6	Fixed synthesis of functions in latched blocks	2013-05-16 16:44:06 +02:00
Clifford Wolf	b56e06d2f5	Added support for verilog === operator	2013-05-07 14:35:40 +02:00
Clifford Wolf	8f2d90de4f	Fixed handling of positional module parameters	2013-04-26 14:40:25 +02:00
Clifford Wolf	453a29c9f6	Only use sha1 checksums for names of parametric modules when the verbose form is to long	2013-04-26 13:13:58 +02:00
Clifford Wolf	e0c408cb4a	Fixed a bug in AST frontend for cases with non-blocking assigned variables as case values	2013-04-13 21:19:10 +02:00
Clifford Wolf	f1a2fd966f	Now only use value from "initial" when no matching "always" block is found	2013-03-31 11:51:12 +02:00
Clifford Wolf	161565be10	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	2013-03-31 11:19:11 +02:00
Clifford Wolf	7bfc7b61a8	Implemented proper handling of stub placeholder modules	2013-03-28 09:20:10 +01:00
Clifford Wolf	7a99349de4	Improvements and bugfixes for generate blocks with local signals	2013-03-26 11:31:34 +01:00
Clifford Wolf	6a382f2aba	Fixed handling of unconditional generate blocks	2013-03-26 09:44:54 +01:00
Clifford Wolf	227520f94d	Added nosync attribute and some async reset related fixes	2013-03-25 17:13:14 +01:00
Clifford Wolf	df9753d398	Added mem2reg option to verilog frontend	2013-03-24 11:13:32 +01:00
Clifford Wolf	3a5244e913	Another fix in mem2reg ast simplify logic	2013-03-24 10:42:08 +01:00
Clifford Wolf	bb3357c027	Improved mem2reg handling in ast simplifier	2013-03-24 09:27:01 +01:00
Clifford Wolf	e45d1c8865	Tiny fixes to verilog parser	2013-03-23 18:54:31 +01:00
Clifford Wolf	8a6b0a3520	Added help messages to ilang and verilog frontends	2013-03-01 08:03:00 +01:00
Clifford Wolf	a321a5c412	Moved stand-alone libs to libs/ directory and added libs/subcircuit	2013-02-27 09:32:19 +01:00
Clifford Wolf	4f0c2862a0	Added support for verilog genblock[index].member syntax	2013-02-26 13:18:22 +01:00
Clifford Wolf	6d1502b948	Added support for "always @(*)"	2013-01-16 17:32:11 +01:00
Clifford Wolf	6543917fb8	added .gitignore files	2013-01-05 11:19:11 +01:00
Clifford Wolf	7764d0ba1d	initial import	2013-01-05 11:13:26 +01:00