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Clifford Wolf 2013-01-05 11:13:26 +01:00
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frontends/ast/Makefile.inc Normal file
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OBJS += frontends/ast/ast.o
OBJS += frontends/ast/simplify.o
OBJS += frontends/ast/genrtlil.o

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frontends/ast/ast.cc Normal file
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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* ---
*
* This is the AST frontend library.
*
* The AST frontend library is not a frontend on it's own but provides a
* generic abstract syntax tree (AST) abstraction for HDL code and can be
* used by HDL frontends. See "ast.h" for an overview of the API and the
* Verilog frontend for an usage example.
*
*/
#include "kernel/log.h"
#include "kernel/sha1.h"
#include "ast.h"
#include <sstream>
#include <stdarg.h>
#include <assert.h>
using namespace AST;
using namespace AST_INTERNAL;
// instanciate global variables (public API)
namespace AST {
std::string current_filename;
void (*set_line_num)(int) = NULL;
int (*get_line_num)() = NULL;
}
// instanciate global variables (private API)
namespace AST_INTERNAL {
bool flag_dump_ast, flag_dump_ast_diff, flag_dump_vlog, flag_nolatches, flag_nomem2reg;
AstNode *current_ast, *current_ast_mod;
std::map<std::string, AstNode*> current_scope;
RTLIL::SigSpec *genRTLIL_subst_from = NULL;
RTLIL::SigSpec *genRTLIL_subst_to = NULL;
AstNode *current_top_block, *current_block, *current_block_child;
AstModule *current_module;
}
// convert node types to string
std::string AST::type2str(AstNodeType type)
{
switch (type)
{
#define X(_item) case _item: return #_item;
X(AST_NONE)
X(AST_DESIGN)
X(AST_MODULE)
X(AST_TASK)
X(AST_FUNCTION)
X(AST_WIRE)
X(AST_MEMORY)
X(AST_AUTOWIRE)
X(AST_PARAMETER)
X(AST_LOCALPARAM)
X(AST_PARASET)
X(AST_ARGUMENT)
X(AST_RANGE)
X(AST_CONSTANT)
X(AST_CELLTYPE)
X(AST_IDENTIFIER)
X(AST_FCALL)
X(AST_TO_SIGNED)
X(AST_TO_UNSIGNED)
X(AST_CONCAT)
X(AST_REPLICATE)
X(AST_BIT_NOT)
X(AST_BIT_AND)
X(AST_BIT_OR)
X(AST_BIT_XOR)
X(AST_BIT_XNOR)
X(AST_REDUCE_AND)
X(AST_REDUCE_OR)
X(AST_REDUCE_XOR)
X(AST_REDUCE_XNOR)
X(AST_REDUCE_BOOL)
X(AST_SHIFT_LEFT)
X(AST_SHIFT_RIGHT)
X(AST_SHIFT_SLEFT)
X(AST_SHIFT_SRIGHT)
X(AST_LT)
X(AST_LE)
X(AST_EQ)
X(AST_NE)
X(AST_GE)
X(AST_GT)
X(AST_ADD)
X(AST_SUB)
X(AST_MUL)
X(AST_DIV)
X(AST_MOD)
X(AST_POW)
X(AST_POS)
X(AST_NEG)
X(AST_LOGIC_AND)
X(AST_LOGIC_OR)
X(AST_LOGIC_NOT)
X(AST_TERNARY)
X(AST_MEMRD)
X(AST_MEMWR)
X(AST_TCALL)
X(AST_ASSIGN)
X(AST_CELL)
X(AST_PRIMITIVE)
X(AST_ALWAYS)
X(AST_BLOCK)
X(AST_ASSIGN_EQ)
X(AST_ASSIGN_LE)
X(AST_CASE)
X(AST_COND)
X(AST_DEFAULT)
X(AST_FOR)
X(AST_GENVAR)
X(AST_GENFOR)
X(AST_GENIF)
X(AST_GENBLOCK)
X(AST_POSEDGE)
X(AST_NEGEDGE)
X(AST_EDGE)
#undef X
default:
assert(!"Missing enum to string def in AST::type2str().");
abort();
}
}
// create new node (AstNode constructor)
// (the optional child arguments make it easier to create AST trees)
AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2)
{
this->type = type;
filename = current_filename;
linenum = get_line_num();
is_input = false;
is_output = false;
is_reg = false;
is_signed = false;
range_valid = false;
port_id = 0;
range_left = -1;
range_right = 0;
integer = 0;
id2ast = NULL;
if (child1)
children.push_back(child1);
if (child2)
children.push_back(child2);
}
// create a (deep recursive) copy of a node
AstNode *AstNode::clone()
{
AstNode *that = new AstNode;
*that = *this;
for (auto &it : that->children)
it = it->clone();
for (auto &it : that->attributes)
it.second = it.second->clone();
return that;
}
// create a (deep recursive) copy of a node use 'other' as target root node
void AstNode::cloneInto(AstNode *other)
{
AstNode *tmp = clone();
other->delete_children();
*other = *tmp;
tmp->children.clear();
tmp->attributes.clear();
delete tmp;
}
// delete all children in this node
void AstNode::delete_children()
{
for (auto &it : children)
delete it;
children.clear();
for (auto &it : attributes)
delete it.second;
attributes.clear();
}
// AstNode destructor
AstNode::~AstNode()
{
delete_children();
}
// create a nice text representation of the node
// (traverse tree by recursion, use 'other' pointer for diffing two AST trees)
void AstNode::dumpAst(FILE *f, std::string indent, AstNode *other)
{
if (f == NULL) {
for (auto f : log_files)
dumpAst(f, indent, other);
return;
}
if (other != NULL) {
if (type != other->type)
goto found_diff_to_other;
if (children.size() != other->children.size())
goto found_diff_to_other;
if (str != other->str)
goto found_diff_to_other;
if (bits != other->bits)
goto found_diff_to_other;
if (is_input != other->is_input)
goto found_diff_to_other;
if (is_output != other->is_output)
goto found_diff_to_other;
if (is_reg != other->is_reg)
goto found_diff_to_other;
if (is_signed != other->is_signed)
goto found_diff_to_other;
if (range_valid != other->range_valid)
goto found_diff_to_other;
if (port_id != other->port_id)
goto found_diff_to_other;
if (range_left != other->range_left)
goto found_diff_to_other;
if (range_right != other->range_right)
goto found_diff_to_other;
if (integer != other->integer)
goto found_diff_to_other;
if (0) {
found_diff_to_other:
other->dumpAst(f, indent + "- ");
this->dumpAst(f, indent + "+ ");
return;
}
}
std::string type_name = type2str(type);
fprintf(f, "%s%s <%s:%d>", indent.c_str(), type_name.c_str(), filename.c_str(), linenum);
if (!str.empty())
fprintf(f, " str='%s'", str.c_str());
if (!bits.empty()) {
fprintf(f, " bits='");
for (size_t i = bits.size(); i > 0; i--)
fprintf(f, "%c", bits[i-1] == RTLIL::S0 ? '0' :
bits[i-1] == RTLIL::S1 ? '1' :
bits[i-1] == RTLIL::Sx ? 'x' :
bits[i-1] == RTLIL::Sz ? 'z' : '?');
fprintf(f, "'(%zd)", bits.size());
}
if (is_input)
fprintf(f, " input");
if (is_output)
fprintf(f, " output");
if (is_reg)
fprintf(f, " reg");
if (is_signed)
fprintf(f, " signed");
if (port_id > 0)
fprintf(f, " port=%d", port_id);
if (range_valid || range_left != -1 || range_right != 0)
fprintf(f, " range=[%d:%d]%s", range_left, range_right, range_valid ? "" : "!");
if (integer != 0)
fprintf(f, " int=%u", (int)integer);
fprintf(f, "\n");
for (size_t i = 0; i < children.size(); i++)
children[i]->dumpAst(f, indent + " ", other ? other->children[i] : NULL);
}
// helper function for AstNode::dumpVlog()
static std::string id2vl(std::string txt)
{
if (txt.size() > 1 && txt[0] == '\\')
txt = txt.substr(1);
for (size_t i = 0; i < txt.size(); i++) {
if ('A' <= txt[i] && txt[i] <= 'Z') continue;
if ('a' <= txt[i] && txt[i] <= 'z') continue;
if ('0' <= txt[i] && txt[i] <= '9') continue;
if (txt[i] == '_') continue;
txt = "\\" + txt + " ";
break;
}
return txt;
}
// dump AST node as verilog pseudo-code
void AstNode::dumpVlog(FILE *f, std::string indent)
{
bool first = true;
std::string txt;
std::vector<AstNode*> rem_children1, rem_children2;
if (f == NULL) {
for (auto f : log_files)
dumpVlog(f, indent);
return;
}
switch (type)
{
case AST_MODULE:
fprintf(f, "%s" "module %s(", indent.c_str(), id2vl(str).c_str());
for (auto child : children)
if (child->type == AST_WIRE && (child->is_input || child->is_output)) {
fprintf(f, "%s%s", first ? "" : ", ", id2vl(child->str).c_str());
first = false;
}
fprintf(f, ");\n");
for (auto child : children)
if (child->type == AST_PARAMETER || child->type == AST_LOCALPARAM)
child->dumpVlog(f, indent + " ");
else
rem_children1.push_back(child);
for (auto child : rem_children1)
if (child->type == AST_WIRE || child->type == AST_AUTOWIRE || child->type == AST_MEMORY)
child->dumpVlog(f, indent + " ");
else
rem_children2.push_back(child);
rem_children1.clear();
for (auto child : rem_children2)
if (child->type == AST_TASK || child->type == AST_FUNCTION)
child->dumpVlog(f, indent + " ");
else
rem_children1.push_back(child);
rem_children2.clear();
for (auto child : rem_children1)
child->dumpVlog(f, indent + " ");
rem_children1.clear();
fprintf(f, "%s" "endmodule\n", indent.c_str());
break;
case AST_WIRE:
if (is_input && is_output)
fprintf(f, "%s" "inout", indent.c_str());
else if (is_input)
fprintf(f, "%s" "input", indent.c_str());
else if (is_output)
fprintf(f, "%s" "output", indent.c_str());
else if (!is_reg)
fprintf(f, "%s" "wire", indent.c_str());
if (is_reg)
fprintf(f, "%s" "reg", (is_input || is_output) ? " " : indent.c_str());
if (is_signed)
fprintf(f, " signed");
for (auto child : children) {
fprintf(f, " ");
child->dumpVlog(f, "");
}
fprintf(f, " %s", id2vl(str).c_str());
fprintf(f, ";\n");
break;
case AST_MEMORY:
fprintf(f, "%s" "memory", indent.c_str());
if (is_signed)
fprintf(f, " signed");
for (auto child : children) {
fprintf(f, " ");
child->dumpVlog(f, "");
if (first)
fprintf(f, " %s", id2vl(str).c_str());
first = false;
}
fprintf(f, ";\n");
break;
case AST_RANGE:
if (range_valid)
fprintf(f, "[%d:%d]", range_left, range_right);
else {
for (auto child : children) {
fprintf(f, "%c", first ? '[' : ':');
child->dumpVlog(f, "");
first = false;
}
fprintf(f, "]");
}
break;
case AST_ALWAYS:
fprintf(f, "%s" "always @(", indent.c_str());
for (auto child : children) {
if (child->type != AST_POSEDGE && child->type != AST_NEGEDGE && child->type != AST_EDGE)
continue;
if (!first)
fprintf(f, ", ");
child->dumpVlog(f, "");
first = false;
}
fprintf(f, ")\n");
for (auto child : children) {
if (child->type != AST_POSEDGE && child->type != AST_NEGEDGE && child->type != AST_EDGE)
child->dumpVlog(f, indent + " ");
}
break;
case AST_POSEDGE:
case AST_NEGEDGE:
case AST_EDGE:
if (type == AST_POSEDGE)
fprintf(f, "posedge ");
if (type == AST_NEGEDGE)
fprintf(f, "negedge ");
for (auto child : children)
child->dumpVlog(f, "");
break;
case AST_IDENTIFIER:
fprintf(f, "%s", id2vl(str).c_str());
for (auto child : children)
child->dumpVlog(f, "");
break;
case AST_CONSTANT:
if (!str.empty())
fprintf(f, "\"%s\"", str.c_str());
else if (bits.size() == 32)
fprintf(f, "%d", RTLIL::Const(bits).as_int());
else
fprintf(f, "%zd'b %s", bits.size(), RTLIL::Const(bits).as_string().c_str());
break;
case AST_BLOCK:
if (children.size() == 1) {
children[0]->dumpVlog(f, indent);
} else {
fprintf(f, "%s" "begin\n", indent.c_str());
for (auto child : children)
child->dumpVlog(f, indent + " ");
fprintf(f, "%s" "end\n", indent.c_str());
}
break;
case AST_CASE:
fprintf(f, "%s" "case (", indent.c_str());
children[0]->dumpVlog(f, "");
fprintf(f, ")\n");
for (size_t i = 1; i < children.size(); i++) {
AstNode *child = children[i];
child->dumpVlog(f, indent + " ");
}
fprintf(f, "%s" "endcase\n", indent.c_str());
break;
case AST_COND:
for (auto child : children) {
if (child->type == AST_BLOCK) {
fprintf(f, ":\n");
child->dumpVlog(f, indent + " ");
first = true;
} else {
fprintf(f, "%s", first ? indent.c_str() : ", ");
if (child->type == AST_DEFAULT)
fprintf(f, "default");
else
child->dumpVlog(f, "");
first = false;
}
}
break;
case AST_ASSIGN_EQ:
case AST_ASSIGN_LE:
fprintf(f, "%s", indent.c_str());
children[0]->dumpVlog(f, "");
fprintf(f, " %s ", type == AST_ASSIGN_EQ ? "=" : "<=");
children[1]->dumpVlog(f, "");
fprintf(f, ";\n");
break;
case AST_CONCAT:
fprintf(f, "{");
for (auto child : children) {
if (!first)
fprintf(f, ", ");
child->dumpVlog(f, "");
first = false;
}
fprintf(f, "}");
break;
case AST_REPLICATE:
fprintf(f, "{");
children[0]->dumpVlog(f, "");
fprintf(f, "{");
children[1]->dumpVlog(f, "");
fprintf(f, "}}");
break;
if (0) { case AST_BIT_NOT: txt = "~"; }
if (0) { case AST_REDUCE_AND: txt = "&"; }
if (0) { case AST_REDUCE_OR: txt = "|"; }
if (0) { case AST_REDUCE_XOR: txt = "^"; }
if (0) { case AST_REDUCE_XNOR: txt = "~^"; }
if (0) { case AST_REDUCE_BOOL: txt = "|"; }
if (0) { case AST_POS: txt = "+"; }
if (0) { case AST_NEG: txt = "-"; }
if (0) { case AST_LOGIC_NOT: txt = "!"; }
fprintf(f, "%s(", txt.c_str());
children[0]->dumpVlog(f, "");
fprintf(f, ")");
break;
if (0) { case AST_BIT_AND: txt = "&"; }
if (0) { case AST_BIT_OR: txt = "|"; }
if (0) { case AST_BIT_XOR: txt = "^"; }
if (0) { case AST_BIT_XNOR: txt = "~^"; }
if (0) { case AST_SHIFT_LEFT: txt = "<<"; }
if (0) { case AST_SHIFT_RIGHT: txt = ">>"; }
if (0) { case AST_SHIFT_SLEFT: txt = "<<<"; }
if (0) { case AST_SHIFT_SRIGHT: txt = ">>>"; }
if (0) { case AST_LT: txt = "<"; }
if (0) { case AST_LE: txt = "<="; }
if (0) { case AST_EQ: txt = "=="; }
if (0) { case AST_NE: txt = "!="; }
if (0) { case AST_GE: txt = ">="; }
if (0) { case AST_GT: txt = ">"; }
if (0) { case AST_ADD: txt = "+"; }
if (0) { case AST_SUB: txt = "-"; }
if (0) { case AST_MUL: txt = "*"; }
if (0) { case AST_DIV: txt = "/"; }
if (0) { case AST_MOD: txt = "%"; }
if (0) { case AST_POW: txt = "**"; }
if (0) { case AST_LOGIC_AND: txt = "&&"; }
if (0) { case AST_LOGIC_OR: txt = "||"; }
fprintf(f, "(");
children[0]->dumpVlog(f, "");
fprintf(f, ")%s(", txt.c_str());
children[1]->dumpVlog(f, "");
fprintf(f, ")");
break;
case AST_TERNARY:
fprintf(f, "(");
children[0]->dumpVlog(f, "");
fprintf(f, ") ? (");
children[1]->dumpVlog(f, "");
fprintf(f, ") : (");
children[2]->dumpVlog(f, "");
fprintf(f, ")");
break;
default:
std::string type_name = type2str(type);
fprintf(f, "%s" "/** %s **/%s", indent.c_str(), type_name.c_str(), indent.empty() ? "" : "\n");
// dumpAst(f, indent, NULL);
}
}
// check if two AST nodes are identical
bool AstNode::operator==(const AstNode &other) const
{
if (type != other.type)
return false;
if (children.size() != other.children.size())
return false;
if (str != other.str)
return false;
if (bits != other.bits)
return false;
if (is_input != other.is_input)
return false;
if (is_output != other.is_output)
return false;
if (is_reg != other.is_reg)
return false;
if (is_signed != other.is_signed)
return false;
if (range_valid != other.range_valid)
return false;
if (port_id != other.port_id)
return false;
if (range_left != other.range_left)
return false;
if (range_right != other.range_right)
return false;
if (integer != other.integer)
return false;
for (size_t i = 0; i < children.size(); i++)
if (*children[i] != *other.children[i])
return false;
return true;
}
// check if two AST nodes are not identical
bool AstNode::operator!=(const AstNode &other) const
{
return !(*this == other);
}
// check if this AST contains the given node
bool AstNode::contains(const AstNode *other) const
{
if (this == other)
return true;
for (auto child : children)
if (child->contains(other))
return true;
return false;
}
// create an AST node for a constant (using a 32 bit int as value)
AstNode *AstNode::mkconst_int(uint32_t v, bool is_signed, int width)
{
AstNode *node = new AstNode(AST_CONSTANT);
node->integer = v;
node->is_signed = is_signed;
for (int i = 0; i < width; i++) {
node->bits.push_back((v & 1) ? RTLIL::S1 : RTLIL::S0);
v = v >> 1;
}
node->range_valid = true;
node->range_left = width-1;
node->range_right = 0;
return node;
}
// create an AST node for a constant (using a bit vector as value)
AstNode *AstNode::mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signed)
{
AstNode *node = new AstNode(AST_CONSTANT);
node->is_signed = is_signed;
node->bits = v;
for (size_t i = 0; i < 32; i++) {
if (i < node->bits.size())
node->integer |= (node->bits[i] == RTLIL::S1) << i;
else if (is_signed)
node->integer |= (node->bits.back() == RTLIL::S1) << i;
}
node->range_valid = true;
node->range_left = node->bits.size();
node->range_right = 0;
return node;
}
// create a new AstModule from an AST_MODULE AST node
static AstModule* process_module(AstNode *ast)
{
assert(ast->type == AST_MODULE);
log("Generating RTLIL representation for module `%s'.\n", ast->str.c_str());
current_ast_mod = ast;
AstNode *ast_before_simplify = ast->clone();
while (ast->simplify(false, false, false, 0)) { }
if (flag_dump_ast) {
log("Dumping verilog AST (as requested by %s option):\n", flag_dump_ast_diff ? "dump_ast_diff" : "dump_ast");
ast->dumpAst(NULL, " ", flag_dump_ast_diff ? ast_before_simplify : NULL);
log("--- END OF AST DUMP ---\n");
}
if (flag_dump_vlog) {
log("Dumping verilog AST (as requested by dump_vlog option):\n");
ast->dumpVlog(NULL, " ");
log("--- END OF AST DUMP ---\n");
}
current_module = new AstModule;
current_module->ast = NULL;
current_module->name = ast->str;
current_module->attributes["\\src"] = stringf("%s:%d", ast->filename.c_str(), ast->linenum);
for (auto &attr : ast->attributes) {
if (attr.second->type != AST_CONSTANT)
log_error("Attribute `%s' with non-constant value at %s:%d!\n",
attr.first.c_str(), ast->filename.c_str(), ast->linenum);
current_module->attributes[attr.first].str = attr.second->str;
current_module->attributes[attr.first].bits = attr.second->bits;
}
for (size_t i = 0; i < ast->children.size(); i++) {
AstNode *node = ast->children[i];
if (node->type == AST_WIRE || node->type == AST_MEMORY)
node->genRTLIL();
}
for (size_t i = 0; i < ast->children.size(); i++) {
AstNode *node = ast->children[i];
if (node->type != AST_WIRE && node->type != AST_MEMORY)
node->genRTLIL();
}
current_module->ast = ast_before_simplify;
current_module->nolatches = flag_nolatches;
current_module->nomem2reg = flag_nomem2reg;
return current_module;
}
// create AstModule instances for all modules in the AST tree and add them to 'design'
void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast, bool dump_ast_diff, bool dump_vlog, bool nolatches, bool nomem2reg)
{
current_ast = ast;
flag_dump_ast = dump_ast;
flag_dump_ast_diff = dump_ast_diff;
flag_dump_vlog = dump_vlog;
flag_nolatches = nolatches;
flag_nomem2reg = nomem2reg;
assert(current_ast->type == AST_DESIGN);
for (auto it = current_ast->children.begin(); it != current_ast->children.end(); it++) {
if (design->modules.count((*it)->str) != 0)
log_error("Re-definition of module `%s' at %s:%d!\n",
(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
design->modules[(*it)->str] = process_module(*it);
}
}
// AstModule destructor
AstModule::~AstModule()
{
if (ast != NULL)
delete ast;
}
// create a new parametric module (when needed) and return the name of the generated module
RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map<RTLIL::IdString, RTLIL::Const> parameters)
{
log_header("Executing AST frontend in derive mode using pre-parsed AST for module `%s'.\n", name.c_str());
current_ast = NULL;
flag_dump_ast = false;
flag_dump_ast_diff = false;
flag_dump_vlog = false;
flag_nolatches = nolatches;
flag_nomem2reg = nomem2reg;
use_internal_line_num();
std::vector<unsigned char> hash_data;
hash_data.insert(hash_data.end(), name.begin(), name.end());
hash_data.push_back(0);
AstNode *new_ast = ast->clone();
int para_counter = 0;
for (auto it = new_ast->children.begin(); it != new_ast->children.end(); it++) {
AstNode *child = *it;
if (child->type != AST_PARAMETER)
continue;
para_counter++;
std::string para_id = child->str;
if (parameters.count(child->str) > 0) {
log("Parameter %s = %s\n", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[child->str])));
rewrite_parameter:
child->delete_children();
child->children.push_back(AstNode::mkconst_bits(parameters[para_id].bits, false));
hash_data.insert(hash_data.end(), child->str.begin(), child->str.end());
hash_data.push_back(0);
hash_data.insert(hash_data.end(), parameters[para_id].bits.begin(), parameters[para_id].bits.end());
hash_data.push_back(0xff);
parameters.erase(para_id);
continue;
}
char buf[100];
snprintf(buf, 100, "$%d", para_counter);
if (parameters.count(buf) > 0) {
para_id = buf;
log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id])));
goto rewrite_parameter;
}
}
if (parameters.size() > 0)
log_error("Requested parameter `%s' does not exist in module `%s'!\n", parameters.begin()->first.c_str(), name.c_str());
unsigned char hash[20];
unsigned char *hash_data2 = new unsigned char[hash_data.size()];
for (size_t i = 0; i < hash_data.size(); i++)
hash_data2[i] = hash_data[i];
sha1::calc(hash_data2, hash_data.size(), hash);
delete[] hash_data2;
char hexstring[41];
sha1::toHexString(hash, hexstring);
std::string modname = "$paramod$" + std::string(hexstring) + "$" + name;
if (design->modules.count(modname) == 0) {
new_ast->str = modname;
design->modules[modname] = process_module(new_ast);
} else {
log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());
}
delete new_ast;
return modname;
}
// recompile a module from AST with updated widths for auto-wires
// (auto-wires are wires that are used but not declared an thus have an automatically determined width)
void AstModule::update_auto_wires(std::map<RTLIL::IdString, int> auto_sizes)
{
log_header("Executing AST frontend in update_auto_wires mode using pre-parsed AST for module `%s'.\n", name.c_str());
current_ast = NULL;
flag_dump_ast = false;
flag_dump_ast_diff = false;
flag_dump_vlog = false;
flag_nolatches = nolatches;
flag_nomem2reg = nomem2reg;
use_internal_line_num();
for (auto it = auto_sizes.begin(); it != auto_sizes.end(); it++) {
log("Adding extra wire declaration to AST: wire [%d:0] %s\n", it->second - 1, it->first.c_str());
AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, AstNode::mkconst_int(it->second - 1, true), AstNode::mkconst_int(0, true)));
wire->str = it->first;
ast->children.insert(ast->children.begin(), wire);
}
AstModule *newmod = process_module(ast);
delete ast;
ast = newmod->ast;
newmod->ast = NULL;
wires.swap(newmod->wires);
cells.swap(newmod->cells);
processes.swap(newmod->processes);
connections.swap(newmod->connections);
attributes.swap(newmod->attributes);
delete newmod;
}
// internal dummy line number callbacks
namespace {
int internal_line_num;
void internal_set_line_num(int n) {
internal_line_num = n;
}
int internal_get_line_num() {
return internal_line_num;
}
}
// use internal dummy line number callbacks
void AST::use_internal_line_num()
{
set_line_num = &internal_set_line_num;
get_line_num = &internal_get_line_num;
}

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* ---
*
* This is the AST frontend library.
*
* The AST frontend library is not a frontend on it's own but provides a
* generic abstract syntax tree (AST) abstraction for HDL code and can be
* used by HDL frontends. See "ast.h" for an overview of the API and the
* Verilog frontend for an usage example.
*
*/
#ifndef AST_H
#define AST_H
#include "kernel/rtlil.h"
#include <stdint.h>
#include <set>
namespace AST
{
// all node types, type2str() must be extended
// whenever a new node type is added here
enum AstNodeType
{
AST_NONE,
AST_DESIGN,
AST_MODULE,
AST_TASK,
AST_FUNCTION,
AST_WIRE,
AST_MEMORY,
AST_AUTOWIRE,
AST_PARAMETER,
AST_LOCALPARAM,
AST_PARASET,
AST_ARGUMENT,
AST_RANGE,
AST_CONSTANT,
AST_CELLTYPE,
AST_IDENTIFIER,
AST_FCALL,
AST_TO_SIGNED,
AST_TO_UNSIGNED,
AST_CONCAT,
AST_REPLICATE,
AST_BIT_NOT,
AST_BIT_AND,
AST_BIT_OR,
AST_BIT_XOR,
AST_BIT_XNOR,
AST_REDUCE_AND,
AST_REDUCE_OR,
AST_REDUCE_XOR,
AST_REDUCE_XNOR,
AST_REDUCE_BOOL,
AST_SHIFT_LEFT,
AST_SHIFT_RIGHT,
AST_SHIFT_SLEFT,
AST_SHIFT_SRIGHT,
AST_LT,
AST_LE,
AST_EQ,
AST_NE,
AST_GE,
AST_GT,
AST_ADD,
AST_SUB,
AST_MUL,
AST_DIV,
AST_MOD,
AST_POW,
AST_POS,
AST_NEG,
AST_LOGIC_AND,
AST_LOGIC_OR,
AST_LOGIC_NOT,
AST_TERNARY,
AST_MEMRD,
AST_MEMWR,
AST_TCALL,
AST_ASSIGN,
AST_CELL,
AST_PRIMITIVE,
AST_ALWAYS,
AST_BLOCK,
AST_ASSIGN_EQ,
AST_ASSIGN_LE,
AST_CASE,
AST_COND,
AST_DEFAULT,
AST_FOR,
AST_GENVAR,
AST_GENFOR,
AST_GENIF,
AST_GENBLOCK,
AST_POSEDGE,
AST_NEGEDGE,
AST_EDGE
};
// convert an node type to a string (e.g. for debug output)
std::string type2str(AstNodeType type);
// The AST is built using instances of this struct
struct AstNode
{
// this nodes type
AstNodeType type;
// the list of child nodes for this node
std::vector<AstNode*> children;
// the list of attributes assigned to this node
std::map<RTLIL::IdString, AstNode*> attributes;
// node content - most of it is unused in most node types
std::string str;
std::vector<RTLIL::State> bits;
bool is_input, is_output, is_reg, is_signed, range_valid;
int port_id, range_left, range_right;
uint32_t integer;
// this is set by simplify and used during RTLIL generation
AstNode *id2ast;
// this is the original sourcecode location that resulted in this AST node
// it is automatically set by the constructor using AST::current_filename and
// the AST::get_line_num() callback function.
std::string filename;
int linenum;
// creating and deleting nodes
AstNode(AstNodeType type = AST_NONE, AstNode *child1 = NULL, AstNode *child2 = NULL);
AstNode *clone();
void cloneInto(AstNode *other);
void delete_children();
~AstNode();
// simplify() creates a simpler AST by unrolling for-loops, expanding generate blocks, etc.
// it also sets the id2ast pointers so that identifier lookups are fast in genRTLIL()
bool simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage);
void expand_genblock(std::string index_var, std::string prefix, std::map<std::string, std::string> &name_map);
void replace_ids(std::map<std::string, std::string> &rules);
void mem2reg_as_needed_pass1(std::set<AstNode*> &mem2reg_set, std::set<AstNode*> &mem2reg_candidates, bool sync_proc, bool async_proc);
void mem2reg_as_needed_pass2(std::set<AstNode*> &mem2reg_set, AstNode *mod, AstNode *block);
void meminfo(int &mem_width, int &mem_size, int &addr_bits);
// create a human-readable text representation of the AST (for debugging)
void dumpAst(FILE *f, std::string indent, AstNode *other = NULL);
void dumpVlog(FILE *f, std::string indent);
// create RTLIL code for this AST node
// for expressions the resulting signal vector is returned
// all generated cell instances, etc. are written to the RTLIL::Module pointed to by AST_INTERNAL::current_module
RTLIL::SigSpec genRTLIL(int width_hint = -1);
RTLIL::SigSpec genWidthRTLIL(int width, RTLIL::SigSpec *subst_from = NULL, RTLIL::SigSpec *subst_to = NULL);
// compare AST nodes
bool operator==(const AstNode &other) const;
bool operator!=(const AstNode &other) const;
bool contains(const AstNode *other) const;
// helper functions for creating AST nodes for constants
static AstNode *mkconst_int(uint32_t v, bool is_signed, int width = 32);
static AstNode *mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signed);
};
// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
void process(RTLIL::Design *design, AstNode *ast, bool dump_ast = false, bool dump_ast_diff = false, bool dump_vlog = false, bool nolatches = false, bool nomem2reg = false);
// parametric modules are supported directly by the AST library
// therfore we need our own derivate of RTLIL::Module with overloaded virtual functions
struct AstModule : RTLIL::Module {
AstNode *ast;
bool nolatches, nomem2reg;
virtual ~AstModule();
virtual RTLIL::IdString derive(RTLIL::Design *design, std::map<RTLIL::IdString, RTLIL::Const> parameters);
virtual void update_auto_wires(std::map<RTLIL::IdString, int> auto_sizes);
};
// this must be set by the language frontend before parsing the sources
// the AstNode constructor then uses current_filename and get_line_num()
// to initialize the filename and linenum properties of new nodes
extern std::string current_filename;
extern void (*set_line_num)(int);
extern int (*get_line_num)();
// set set_line_num and get_line_num to internal dummy functions
// (done by simplify(), AstModule::derive and AstModule::update_auto_wires to control
// the filename and linenum properties of new nodes not generated by a frontend parser)
void use_internal_line_num();
}
namespace AST_INTERNAL
{
// internal state variables
extern bool flag_dump_ast, flag_dump_ast_diff, flag_nolatches, flag_nomem2reg;
extern AST::AstNode *current_ast, *current_ast_mod;
extern std::map<std::string, AST::AstNode*> current_scope;
extern RTLIL::SigSpec *genRTLIL_subst_from, *genRTLIL_subst_to;
extern AST::AstNode *current_top_block, *current_block, *current_block_child;
extern AST::AstModule *current_module;
struct ProcessGenerator;
}
#endif

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GENFILES += frontends/ilang/parser.tab.cc
GENFILES += frontends/ilang/parser.tab.h
GENFILES += frontends/ilang/parser.output
GENFILES += frontends/ilang/lexer.cc
frontends/ilang/parser.tab.cc frontends/ilang/parser.tab.h: frontends/ilang/parser.y
bison -d -r all -b frontends/ilang/parser frontends/ilang/parser.y
mv frontends/ilang/parser.tab.c frontends/ilang/parser.tab.cc
frontends/ilang/lexer.cc: frontends/ilang/lexer.l
flex -o frontends/ilang/lexer.cc frontends/ilang/lexer.l
OBJS += frontends/ilang/parser.tab.o frontends/ilang/lexer.o
OBJS += frontends/ilang/ilang_frontend.o

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* ---
*
* A very simple and straightforward frontend for the RTLIL text
* representation (as generated by the 'ilang' backend).
*
*/
#include "ilang_frontend.h"
#include "kernel/register.h"
#include "kernel/log.h"
void rtlil_frontend_ilang_yyerror(char const *s)
{
log_error("Parser error in line %d: %s\n", rtlil_frontend_ilang_yyget_lineno(), s);
}
struct IlangFrontend : public Frontend {
IlangFrontend() : Frontend("ilang") { }
virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing ILANG frontend.\n");
extra_args(f, filename, args, 1);
log("Input filename: %s\n", filename.c_str());
ILANG_FRONTEND::current_design = design;
rtlil_frontend_ilang_yydebug = false;
rtlil_frontend_ilang_yyrestart(f);
rtlil_frontend_ilang_yyparse();
rtlil_frontend_ilang_yylex_destroy();
}
} IlangFrontend;

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* ---
*
* A very simple and straightforward frontend for the RTLIL text
* representation (as generated by the 'ilang' backend).
*
*/
#ifndef ILANG_FRONTEND_H
#define ILANG_FRONTEND_H
#include "kernel/rtlil.h"
#include <stdio.h>
namespace ILANG_FRONTEND {
void ilang_frontend(FILE *f, RTLIL::Design *design);
extern RTLIL::Design *current_design;
}
extern int rtlil_frontend_ilang_yydebug;
int rtlil_frontend_ilang_yylex(void);
void rtlil_frontend_ilang_yyerror(char const *s);
void rtlil_frontend_ilang_yyrestart(FILE *f);
int rtlil_frontend_ilang_yyparse(void);
void rtlil_frontend_ilang_yylex_destroy(void);
int rtlil_frontend_ilang_yyget_lineno(void);
#endif

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* ---
*
* A very simple and straightforward frontend for the RTLIL text
* representation (as generated by the 'ilang' backend).
*
*/
%{
#include "kernel/rtlil.h"
#include "parser.tab.h"
%}
%option yylineno
%option noyywrap
%option nounput
%option prefix="rtlil_frontend_ilang_yy"
%x STRING
%%
"module" { return TOK_MODULE; }
"attribute" { return TOK_ATTRIBUTE; }
"parameter" { return TOK_PARAMETER; }
"wire" { return TOK_WIRE; }
"memory" { return TOK_MEMORY; }
"auto" { return TOK_AUTO; }
"width" { return TOK_WIDTH; }
"offset" { return TOK_OFFSET; }
"size" { return TOK_SIZE; }
"input" { return TOK_INPUT; }
"output" { return TOK_OUTPUT; }
"inout" { return TOK_INOUT; }
"cell" { return TOK_CELL; }
"connect" { return TOK_CONNECT; }
"switch" { return TOK_SWITCH; }
"case" { return TOK_CASE; }
"assign" { return TOK_ASSIGN; }
"sync" { return TOK_SYNC; }
"low" { return TOK_LOW; }
"high" { return TOK_HIGH; }
"posedge" { return TOK_POSEDGE; }
"negedge" { return TOK_NEGEDGE; }
"edge" { return TOK_EDGE; }
"always" { return TOK_ALWAYS; }
"update" { return TOK_UPDATE; }
"process" { return TOK_PROCESS; }
"end" { return TOK_END; }
[a-z]+ { return TOK_INVALID; }
"\\"[^ \t\r\n]+ { rtlil_frontend_ilang_yylval.string = strdup(yytext); return TOK_ID; }
"$"[^ \t\r\n]+ { rtlil_frontend_ilang_yylval.string = strdup(yytext); return TOK_ID; }
"."[0-9]+ { rtlil_frontend_ilang_yylval.string = strdup(yytext); return TOK_ID; }
[0-9]+'[01xzm-]+ { rtlil_frontend_ilang_yylval.string = strdup(yytext); return TOK_VALUE; }
[0-9]+ { rtlil_frontend_ilang_yylval.integer = atoi(yytext); return TOK_INT; }
\" { BEGIN(STRING); }
<STRING>\\. { yymore(); }
<STRING>\" {
BEGIN(0);
char *yystr = strdup(yytext);
yystr[strlen(yytext) - 1] = 0;
int i = 0, j = 0;
while (yystr[i]) {
if (yystr[i] == '\\' && yystr[i + 1]) {
i++;
if (yystr[i] == 'n')
yystr[i] = '\n';
else if (yystr[i] == 't')
yystr[i] = '\t';
else if ('0' <= yystr[i] && yystr[i] <= '7') {
yystr[i] = yystr[i] - '0';
if ('0' <= yystr[i + 1] && yystr[i + 1] <= '7') {
yystr[i + 1] = yystr[i] * 8 + yystr[i + 1] - '0';
i++;
}
if ('0' <= yystr[i + 1] && yystr[i + 1] <= '7') {
yystr[i + 1] = yystr[i] * 8 + yystr[i + 1] - '0';
i++;
}
}
}
yystr[j++] = yystr[i++];
}
yystr[j] = 0;
rtlil_frontend_ilang_yylval.string = yystr;
return TOK_STRING;
}
<STRING>. { yymore(); }
"#"[^\n]*\n /* ignore comments */
[ \t] /* ignore non-newline whitespaces */
[\r\n]+ { return TOK_EOL; }
. { return *yytext; }
%%
// this is a hack to avoid the 'yyinput defined but not used' error msgs
void *rtlil_frontend_ilang_avoid_input_warnings() {
return (void*)&yyinput;
}

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* ---
*
* A very simple and straightforward frontend for the RTLIL text
* representation (as generated by the 'ilang' backend).
*
*/
%{
#include <list>
#include "ilang_frontend.h"
namespace ILANG_FRONTEND {
RTLIL::Design *current_design;
RTLIL::Module *current_module;
RTLIL::Wire *current_wire;
RTLIL::Memory *current_memory;
RTLIL::Cell *current_cell;
RTLIL::Process *current_process;
std::vector<std::vector<RTLIL::SwitchRule*>*> switch_stack;
std::vector<RTLIL::CaseRule*> case_stack;
std::map<RTLIL::IdString, RTLIL::Const> attrbuf;
}
using namespace ILANG_FRONTEND;
%}
%name-prefix="rtlil_frontend_ilang_yy"
%union {
char *string;
int integer;
RTLIL::Const *data;
RTLIL::SigSpec *sigspec;
}
%token <string> TOK_ID TOK_VALUE TOK_STRING
%token <integer> TOK_INT
%token TOK_MODULE TOK_WIRE TOK_WIDTH TOK_INPUT TOK_OUTPUT TOK_INOUT
%token TOK_CELL TOK_CONNECT TOK_SWITCH TOK_CASE TOK_ASSIGN TOK_SYNC
%token TOK_LOW TOK_HIGH TOK_POSEDGE TOK_NEGEDGE TOK_EDGE TOK_ALWAYS
%token TOK_UPDATE TOK_PROCESS TOK_END TOK_INVALID TOK_EOL TOK_OFFSET
%token TOK_PARAMETER TOK_ATTRIBUTE TOK_AUTO TOK_MEMORY TOK_SIZE
%type <sigspec> sigspec sigspec_list
%type <integer> sync_type
%type <data> constant
%expect 0
%debug
%%
input:
optional_eol {
attrbuf.clear();
} design {
if (attrbuf.size() != 0)
rtlil_frontend_ilang_yyerror("dangling attribute");
};
optional_eol:
optional_eol TOK_EOL | /* empty */;
design:
design module |
design attr_stmt |
/* empty */;
module:
TOK_MODULE TOK_ID TOK_EOL {
if (current_design->modules.count($2) != 0)
rtlil_frontend_ilang_yyerror("scope error");
current_module = new RTLIL::Module;
current_module->name = $2;
current_module->attributes = attrbuf;
current_design->modules[$2] = current_module;
attrbuf.clear();
free($2);
} module_body TOK_END {
if (attrbuf.size() != 0)
rtlil_frontend_ilang_yyerror("dangling attribute");
} TOK_EOL;
module_body:
module_body module_stmt |
/* empty */;
module_stmt:
attr_stmt | wire_stmt | memory_stmt | cell_stmt | proc_stmt | conn_stmt;
attr_stmt:
TOK_ATTRIBUTE TOK_ID constant TOK_EOL {
attrbuf[$2] = *$3;
delete $3;
};
wire_stmt:
TOK_WIRE {
current_wire = new RTLIL::Wire;
current_wire->attributes = attrbuf;
attrbuf.clear();
} wire_options TOK_ID TOK_EOL {
if (current_module->wires.count($4) != 0)
rtlil_frontend_ilang_yyerror("scope error");
current_wire->name = $4;
current_module->wires[$4] = current_wire;
free($4);
};
wire_options:
wire_options TOK_AUTO {
current_wire->auto_width = true;
} |
wire_options TOK_WIDTH TOK_INT {
current_wire->width = $3;
} |
wire_options TOK_OFFSET TOK_INT {
current_wire->start_offset = $3;
} |
wire_options TOK_INPUT TOK_INT {
current_wire->port_id = $3;
current_wire->port_input = true;
current_wire->port_output = false;
} |
wire_options TOK_OUTPUT TOK_INT {
current_wire->port_id = $3;
current_wire->port_input = false;
current_wire->port_output = true;
} |
wire_options TOK_INOUT TOK_INT {
current_wire->port_id = $3;
current_wire->port_input = true;
current_wire->port_output = true;
} |
/* empty */;
memory_stmt:
TOK_MEMORY {
current_memory = new RTLIL::Memory;
current_memory->attributes = attrbuf;
attrbuf.clear();
} memory_options TOK_ID TOK_EOL {
if (current_module->memories.count($4) != 0)
rtlil_frontend_ilang_yyerror("scope error");
current_memory->name = $4;
current_module->memories[$4] = current_memory;
free($4);
};
memory_options:
memory_options TOK_WIDTH TOK_INT {
current_wire->width = $3;
} |
memory_options TOK_SIZE TOK_INT {
current_memory->size = $3;
} |
/* empty */;
cell_stmt:
TOK_CELL TOK_ID TOK_ID TOK_EOL {
if (current_module->cells.count($3) != 0)
rtlil_frontend_ilang_yyerror("scope error");
current_cell = new RTLIL::Cell;
current_cell->type = $2;
current_cell->name = $3;
current_cell->attributes = attrbuf;
current_module->cells[$3] = current_cell;
attrbuf.clear();
free($2);
free($3);
} cell_body TOK_END TOK_EOL;
cell_body:
cell_body TOK_PARAMETER TOK_ID constant TOK_EOL {
current_cell->parameters[$3] = *$4;
free($3);
delete $4;
} |
cell_body TOK_CONNECT TOK_ID sigspec TOK_EOL {
if (current_cell->connections.count($3) != 0)
rtlil_frontend_ilang_yyerror("scope error");
current_cell->connections[$3] = *$4;
delete $4;
free($3);
} |
/* empty */;
proc_stmt:
TOK_PROCESS TOK_ID TOK_EOL {
if (current_module->processes.count($2) != 0)
rtlil_frontend_ilang_yyerror("scope error");
current_process = new RTLIL::Process;
current_process->name = $2;
current_process->attributes = attrbuf;
current_module->processes[$2] = current_process;
switch_stack.clear();
switch_stack.push_back(&current_process->root_case.switches);
case_stack.clear();
case_stack.push_back(&current_process->root_case);
free($2);
} case_body sync_list TOK_END TOK_EOL;
switch_stmt:
attr_list TOK_SWITCH sigspec TOK_EOL {
RTLIL::SwitchRule *rule = new RTLIL::SwitchRule;
rule->signal = *$3;
rule->attributes = attrbuf;
switch_stack.back()->push_back(rule);
attrbuf.clear();
delete $3;
} switch_body TOK_END TOK_EOL;
attr_list:
/* empty */ |
attr_list attr_stmt;
switch_body:
switch_body TOK_CASE {
RTLIL::CaseRule *rule = new RTLIL::CaseRule;
switch_stack.back()->back()->cases.push_back(rule);
switch_stack.push_back(&rule->switches);
case_stack.push_back(rule);
} compare_list TOK_EOL case_body {
switch_stack.pop_back();
case_stack.pop_back();
} |
/* empty */;
compare_list:
sigspec {
case_stack.back()->compare.push_back(*$1);
delete $1;
} |
compare_list ',' sigspec {
case_stack.back()->compare.push_back(*$3);
delete $3;
} |
/* empty */;
case_body:
switch_stmt case_body |
assign_stmt case_body |
/* empty */;
assign_stmt:
TOK_ASSIGN sigspec sigspec TOK_EOL {
case_stack.back()->actions.push_back(RTLIL::SigSig(*$2, *$3));
delete $2;
delete $3;
};
sync_list:
sync_list TOK_SYNC sync_type sigspec TOK_EOL {
RTLIL::SyncRule *rule = new RTLIL::SyncRule;
rule->type = RTLIL::SyncType($3);
rule->signal = *$4;
current_process->syncs.push_back(rule);
delete $4;
} update_list |
sync_list TOK_SYNC TOK_ALWAYS TOK_EOL {
RTLIL::SyncRule *rule = new RTLIL::SyncRule;
rule->type = RTLIL::SyncType::STa;
rule->signal = RTLIL::SigSpec();
current_process->syncs.push_back(rule);
} update_list |
/* empty */;
sync_type:
TOK_LOW { $$ = RTLIL::ST0; } |
TOK_HIGH { $$ = RTLIL::ST1; } |
TOK_POSEDGE { $$ = RTLIL::STp; } |
TOK_NEGEDGE { $$ = RTLIL::STn; } |
TOK_EDGE { $$ = RTLIL::STe; };
update_list:
update_list TOK_UPDATE sigspec sigspec TOK_EOL {
current_process->syncs.back()->actions.push_back(RTLIL::SigSig(*$3, *$4));
delete $3;
delete $4;
} |
/* empty */;
constant:
TOK_VALUE {
char *ep;
int width = strtol($1, &ep, 10);
std::list<RTLIL::State> bits;
while (*(++ep) != 0) {
RTLIL::State bit = RTLIL::Sx;
switch (*ep) {
case '0': bit = RTLIL::S0; break;
case '1': bit = RTLIL::S1; break;
case 'x': bit = RTLIL::Sx; break;
case 'z': bit = RTLIL::Sz; break;
case '-': bit = RTLIL::Sa; break;
case 'm': bit = RTLIL::Sm; break;
}
bits.push_front(bit);
}
if (bits.size() == 0)
bits.push_back(RTLIL::Sx);
while ((int)bits.size() < width) {
RTLIL::State bit = bits.back();
if (bit == RTLIL::S1)
bit = RTLIL::S0;
bits.push_back(bit);
}
while ((int)bits.size() > width)
bits.pop_back();
$$ = new RTLIL::Const;
for (auto it = bits.begin(); it != bits.end(); it++)
$$->bits.push_back(*it);
free($1);
} |
TOK_INT {
$$ = new RTLIL::Const($1, 32);
} |
TOK_STRING {
$$ = new RTLIL::Const($1);
free($1);
};
sigspec:
constant {
RTLIL::SigChunk chunk;
chunk.wire = NULL;
chunk.width = $1->bits.size();
chunk.offset = 0;
chunk.data = *$1;
$$ = new RTLIL::SigSpec;
$$->chunks.push_back(chunk);
$$->width = chunk.width;
delete $1;
} |
TOK_ID {
if (current_module->wires.count($1) == 0)
rtlil_frontend_ilang_yyerror("scope error");
RTLIL::SigChunk chunk;
chunk.wire = current_module->wires[$1];
chunk.width = current_module->wires[$1]->width;
chunk.offset = 0;
$$ = new RTLIL::SigSpec;
$$->chunks.push_back(chunk);
$$->width = chunk.width;
free($1);
} |
TOK_ID '[' TOK_INT ']' {
if (current_module->wires.count($1) == 0)
rtlil_frontend_ilang_yyerror("scope error");
RTLIL::SigChunk chunk;
chunk.wire = current_module->wires[$1];
chunk.offset = $3;
chunk.width = 1;
$$ = new RTLIL::SigSpec;
$$->chunks.push_back(chunk);
$$->width = 1;
free($1);
} |
TOK_ID '[' TOK_INT ':' TOK_INT ']' {
if (current_module->wires.count($1) == 0)
rtlil_frontend_ilang_yyerror("scope error");
RTLIL::SigChunk chunk;
chunk.wire = current_module->wires[$1];
chunk.width = $3 - $5 + 1;
chunk.offset = $5;
$$ = new RTLIL::SigSpec;
$$->chunks.push_back(chunk);
$$->width = chunk.width;
free($1);
} |
'{' sigspec_list '}' {
$$ = $2;
};
sigspec_list:
sigspec_list sigspec {
$$ = new RTLIL::SigSpec;
for (auto it = $2->chunks.begin(); it != $2->chunks.end(); it++) {
$$->chunks.push_back(*it);
$$->width += it->width;
}
for (auto it = $1->chunks.begin(); it != $1->chunks.end(); it++) {
$$->chunks.push_back(*it);
$$->width += it->width;
}
delete $1;
delete $2;
} |
/* empty */ {
$$ = new RTLIL::SigSpec;
};
conn_stmt:
TOK_CONNECT sigspec sigspec TOK_EOL {
if (attrbuf.size() != 0)
rtlil_frontend_ilang_yyerror("dangling attribute");
current_module->connections.push_back(RTLIL::SigSig(*$2, *$3));
delete $2;
delete $3;
};

19
frontends/verilog/Makefile.inc Normal file
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GENFILES += frontends/verilog/parser.tab.cc
GENFILES += frontends/verilog/parser.tab.h
GENFILES += frontends/verilog/parser.output
GENFILES += frontends/verilog/lexer.cc
frontends/verilog/parser.tab.cc frontends/verilog/parser.tab.h: frontends/verilog/parser.y
bison -d -r all -b frontends/verilog/parser frontends/verilog/parser.y
mv frontends/verilog/parser.tab.c frontends/verilog/parser.tab.cc
frontends/verilog/lexer.cc: frontends/verilog/lexer.l
flex -o frontends/verilog/lexer.cc frontends/verilog/lexer.l
OBJS += frontends/verilog/parser.tab.o
OBJS += frontends/verilog/lexer.o
OBJS += frontends/verilog/preproc.o
OBJS += frontends/verilog/verilog_frontend.o
OBJS += frontends/verilog/const2ast.o

197
frontends/verilog/const2ast.cc Normal file
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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* ---
*
* The Verilog frontend.
*
* This frontend is using the AST frontend library (see frontends/ast/).
* Thus this frontend does not generate RTLIL code directly but creates an
* AST directly from the Verilog parse tree and then passes this AST to
* the AST frontend library.
*
* ---
*
* This file contains an ad-hoc parser for Verilog constants. The Verilog
* lexer does only recognize a constant but does not actually split it to its
* components. I.e. it just passes the Verilog code for the constant to the
* bison parser. The parser then uses the function const2ast() from this file
* to create an AST node for the constant.
*
*/
#include "verilog_frontend.h"
#include "kernel/log.h"
#include <assert.h>
#include <string.h>
#include <math.h>
using namespace AST;
// divide an arbitrary length decimal number by two and return the rest
static int my_decimal_div_by_two(std::vector<uint8_t> &digits)
{
int carry = 0;
for (size_t i = 0; i < digits.size(); i++) {
assert(digits[i] < 10);
digits[i] += carry * 10;
carry = digits[i] % 2;
digits[i] /= 2;
}
return carry;
}
// find the number of significant bits in a binary number (not including the sign bit)
static int my_ilog2(int x)
{
int ret = 0;
while (x != 0 && x != -1) {
x = x >> 1;
ret++;
}
return ret;
}
// parse a binary, decimal, hexadecimal or octal number with support for special bits ('x', 'z' and '?')
static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int len_in_bits, int base, char case_type)
{
// all digits in string (MSB at index 0)
std::vector<uint8_t> digits;
while (*str) {
if ('0' <= *str && *str <= '9')
digits.push_back(*str - '0');
else if ('a' <= *str && *str <= 'f')
digits.push_back(10 + *str - 'a');
else if ('A' <= *str && *str <= 'F')
digits.push_back(10 + *str - 'A');
else if (*str == 'x' || *str == 'X')
digits.push_back(0xf0);
else if (*str == 'z' || *str == 'Z')
digits.push_back(0xf1);
else if (*str == '?')
digits.push_back(0xf2);
str++;
}
if (base == 10) {
data.clear();
if (len_in_bits < 0)
len_in_bits = ceil(digits.size()/log10(2));
for (int i = 0; i < len_in_bits; i++)
data.push_back(my_decimal_div_by_two(digits) ? RTLIL::S1 : RTLIL::S0);
return;
}
int bits_per_digit = my_ilog2(base-1);
if (len_in_bits < 0)
len_in_bits = digits.size() * bits_per_digit;
data.clear();
data.resize(len_in_bits);
for (int i = 0; i < len_in_bits; i++) {
int bitmask = 1 << (i % bits_per_digit);
int digitidx = digits.size() - (i / bits_per_digit) - 1;
if (digitidx < 0) {
if (i > 0 && (data[i-1] == RTLIL::Sz || data[i-1] == RTLIL::Sx || data[i-1] == RTLIL::Sa))
data[i] = data[i-1];
else
data[i] = RTLIL::S0;
} else if (digits[digitidx] == 0xf0)
data[i] = case_type == 'x' ? RTLIL::Sa : RTLIL::Sx;
else if (digits[digitidx] == 0xf1)
data[i] = case_type == 'x' || case_type == 'z' ? RTLIL::Sa : RTLIL::Sz;
else if (digits[digitidx] == 0xf2)
data[i] = RTLIL::Sa;
else
data[i] = (digits[digitidx] & bitmask) ? RTLIL::S1 : RTLIL::S0;
}
}
// convert the verilog code for a constant to an AST node
AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type)
{
const char *str = code.c_str();
// Strings
if (*str == '"') {
int len = strlen(str) - 2;
std::vector<RTLIL::State> data;
data.reserve(len * 8);
for (int i = 0; i < len; i++) {
unsigned char ch = str[len - i];
for (int j = 0; j < 8; j++) {
data.push_back((ch & 1) ? RTLIL::S1 : RTLIL::S0);
ch = ch >> 1;
}
}
AstNode *ast = AstNode::mkconst_bits(data, false);
ast->str = code;
return ast;
}
for (size_t i = 0; i < code.size(); i++)
if (code[i] == '_' || code[i] == ' ' || code[i] == '\t' || code[i] == '\r' || code[i] == '\n')
code.erase(code.begin()+(i--));
str = code.c_str();
char *endptr;
long intval = strtol(str, &endptr, 10);
// Simple 32 bit integer
if (*endptr == 0)
return AstNode::mkconst_int(intval, true);
// variable length constant
if (str == endptr)
intval = -1;
// The "<bits>'[bodh]<digits>" syntax
if (*endptr == '\'')
{
int len_in_bits = intval;
std::vector<RTLIL::State> data;
bool is_signed = false;
if (*(endptr+1) == 's') {
is_signed = true;
endptr++;
}
switch (*(endptr+1))
{
case 'b':
my_strtobin(data, endptr+2, len_in_bits, 2, case_type);
break;
case 'o':
my_strtobin(data, endptr+2, len_in_bits, 8, case_type);
break;
case 'd':
my_strtobin(data, endptr+2, len_in_bits, 10, case_type);
break;
case 'h':
my_strtobin(data, endptr+2, len_in_bits, 16, case_type);
break;
default:
goto error;
}
return AstNode::mkconst_bits(data, is_signed);
}
error:
log_error("Value conversion failed: `%s'\n", code.c_str());
}

264
frontends/verilog/lexer.l Normal file
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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* ---
*
* The Verilog frontend.
*
* This frontend is using the AST frontend library (see frontends/ast/).
* Thus this frontend does not generate RTLIL code directly but creates an
* AST directly from the Verilog parse tree and then passes this AST to
* the AST frontend library.
*
* ---
*
* A simple lexer for Verilog code. Non-preprocessor compiler directives are
* handled here. The preprocessor stuff is handled in preproc.cc. Everything
* else is left to the bison parser (see parser.y).
*
*/
%{
#include "kernel/log.h"
#include "verilog_frontend.h"
#include "frontends/ast/ast.h"
#include "parser.tab.h"
using namespace AST;
using namespace VERILOG_FRONTEND;
namespace VERILOG_FRONTEND {
std::vector<std::string> fn_stack;
std::vector<int> ln_stack;
bool lexer_feature_defattr;
}
%}
%option yylineno
%option noyywrap
%option nounput
%option prefix="frontend_verilog_yy"
%x COMMENT
%x STRING
%x SYNOPSYS_TRANSLATE_OFF
%x SYNOPSYS_FLAGS
%%
"`file_push "[^\n]* {
fn_stack.push_back(current_filename);
ln_stack.push_back(frontend_verilog_yyget_lineno());
current_filename = yytext+11;
frontend_verilog_yyset_lineno(0);
}
"`file_pop"[^\n]*\n {
current_filename = fn_stack.back();
frontend_verilog_yyset_lineno(ln_stack.back());
}
"`file_notfound "[^\n]* {
log_error("Can't open include file `%s'!\n", yytext + 15);
}
"`timescale"[ \t]+[^ \t\r\n/]+[ \t]*"/"[ \t]*[^ \t\r\n]* /* ignore timescale directive */
"`yosys_enable_defattr" lexer_feature_defattr = true;
"`yosys_disable_defattr" lexer_feature_defattr = false;
"`"[a-zA-Z_$][a-zA-Z0-9_$]* {
frontend_verilog_yyerror("Unimplemented compiler directive or undefined macro %s.", yytext);
}
"module" { return TOK_MODULE; }
"endmodule" { return TOK_ENDMODULE; }
"function" { return TOK_FUNCTION; }
"endfunction" { return TOK_ENDFUNCTION; }
"task" { return TOK_TASK; }
"endtask" { return TOK_ENDTASK; }
"parameter" { return TOK_PARAMETER; }
"localparam" { return TOK_LOCALPARAM; }
"assign" { return TOK_ASSIGN; }
"always" { return TOK_ALWAYS; }
"initial" { return TOK_INITIAL; }
"begin" { return TOK_BEGIN; }
"end" { return TOK_END; }
"if" { return TOK_IF; }
"else" { return TOK_ELSE; }
"for" { return TOK_FOR; }
"posedge" { return TOK_POSEDGE; }
"negedge" { return TOK_NEGEDGE; }
"or" { return TOK_OR; }
"case" { return TOK_CASE; }
"casex" { return TOK_CASEX; }
"casez" { return TOK_CASEZ; }
"endcase" { return TOK_ENDCASE; }
"default" { return TOK_DEFAULT; }
"generate" { return TOK_GENERATE; }
"endgenerate" { return TOK_ENDGENERATE; }
"input" { return TOK_INPUT; }
"output" { return TOK_OUTPUT; }
"inout" { return TOK_INOUT; }
"wire" { return TOK_WIRE; }
"reg" { return TOK_REG; }
"integer" { return TOK_INTEGER; }
"signed" { return TOK_SIGNED; }
"genvar" { return TOK_GENVAR; }
[0-9]+ {
frontend_verilog_yylval.string = new std::string(yytext);
return TOK_CONST;
}
[0-9]*[ \t]*\'s?[bodh][ \t\r\n]*[0-9a-fA-FzxZX?_]+ {
frontend_verilog_yylval.string = new std::string(yytext);
return TOK_CONST;
}
\" { BEGIN(STRING); }
<STRING>\\. { yymore(); }
<STRING>\" {
BEGIN(0);
char *yystr = strdup(yytext);
yystr[strlen(yytext) - 1] = 0;
int i = 0, j = 0;
while (yystr[i]) {
if (yystr[i] == '\\' && yystr[i + 1]) {
i++;
if (yystr[i] == 'n')
yystr[i] = '\n';
else if (yystr[i] == 't')
yystr[i] = '\t';
else if ('0' <= yystr[i] && yystr[i] <= '7') {
yystr[i] = yystr[i] - '0';
if ('0' <= yystr[i + 1] && yystr[i + 1] <= '7') {
yystr[i + 1] = yystr[i] * 8 + yystr[i + 1] - '0';
i++;
}
if ('0' <= yystr[i + 1] && yystr[i + 1] <= '7') {
yystr[i + 1] = yystr[i] * 8 + yystr[i + 1] - '0';
i++;
}
}
}
yystr[j++] = yystr[i++];
}
yystr[j] = 0;
frontend_verilog_yylval.string = new std::string(yystr);
free(yystr);
return TOK_STRING;
}
<STRING>. { yymore(); }
and|nand|or|nor|xor|xnor|not|buf {
frontend_verilog_yylval.string = new std::string(yytext);
return TOK_PRIMITIVE;
}
supply0 { return TOK_SUPPLY0; }
supply1 { return TOK_SUPPLY1; }
"$"(display|time|stop|finish) {
frontend_verilog_yylval.string = new std::string(yytext);
return TOK_ID;
}
"$signed" { return TOK_TO_SIGNED; }
"$unsigned" { return TOK_TO_UNSIGNED; }
[a-zA-Z_$][a-zA-Z0-9_$]* {
frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext);
return TOK_ID;
}
"/*"[ \t]*synopsys[ \t]*translate_off[ \t]*"*/" {
log("Warning: Found one of those horrible `synopsys translate_off' comments.\n");
log("It is strongly suggested to use `ifdef constructs instead!\n");
BEGIN(SYNOPSYS_TRANSLATE_OFF);
}
<SYNOPSYS_TRANSLATE_OFF>. /* ignore synopsys translate_off body */
<SYNOPSYS_TRANSLATE_OFF>\n /* ignore synopsys translate_off body */
<SYNOPSYS_TRANSLATE_OFF>"/*"[ \t]*"synopsys"[ \t]*"translate_on"[ \t]*"*/" { BEGIN(0); }
"/*"[ \t]*"synopsys"[ \t]+ {
BEGIN(SYNOPSYS_FLAGS);
}
<SYNOPSYS_FLAGS>full_case {
log("Warning: Found one of those horrible `synopsys full_case' comments.\n");
log("It is strongly suggested to use verilog x-values and default branches instead!\n");
return TOK_SYNOPSYS_FULL_CASE;
}
<SYNOPSYS_FLAGS>parallel_case {
log("Warning: Found one of those horrible `synopsys parallel_case' comments.\n");
log("It is strongly suggested to use verilog `parallel_case' attributes instead!\n");
return TOK_SYNOPSYS_PARALLEL_CASE;
}
<SYNOPSYS_FLAGS>. /* ignore everything else */
<SYNOPSYS_FLAGS>"*/" { BEGIN(0); }
"\\"[^ \t\r\n]+ {
frontend_verilog_yylval.string = new std::string(yytext);
return TOK_ID;
}
"(*" { return ATTR_BEGIN; }
"*)" { return ATTR_END; }
"{*" { if (lexer_feature_defattr) return DEFATTR_BEGIN; else REJECT; }
"*}" { if (lexer_feature_defattr) return DEFATTR_END; else REJECT; }
"**" { return OP_POW; }
"||" { return OP_LOR; }
"&&" { return OP_LAND; }
"==" { return OP_EQ; }
"!=" { return OP_NE; }
"<=" { return OP_LE; }
">=" { return OP_GE; }
/* "~&" { return OP_NAND; } */
/* "~|" { return OP_NOR; } */
"~^" { return OP_XNOR; }
"^~" { return OP_XNOR; }
"<<" { return OP_SHL; }
">>" { return OP_SHR; }
"<<<" { return OP_SSHL; }
">>>" { return OP_SSHR; }
"/*" { BEGIN(COMMENT); }
<COMMENT>. /* ignore comment body */
<COMMENT>\n /* ignore comment body */
<COMMENT>"*/" { BEGIN(0); }
[ \t\r\n] /* ignore whitespaces */
\\[\r\n] /* ignore continuation sequence */
"//"[^\r\n]* /* ignore one-line comments */
"#"[$a-zA-Z_0-9\.]+ /* ignore simulation timings */
. { return *yytext; }
%%
// this is a hack to avoid the 'yyinput defined but not used' error msgs
void *frontend_verilog_avoid_input_warnings() {
return (void*)&yyinput;
}

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* ---
*
* The Verilog frontend.
*
* This frontend is using the AST frontend library (see frontends/ast/).
* Thus this frontend does not generate RTLIL code directly but creates an
* AST directly from the Verilog parse tree and then passes this AST to
* the AST frontend library.
*
* ---
*
* Ad-hoc implementation of a Verilog preprocessor. The directives `define,
* `include, `ifdef, `ifndef, `else and `endif are handled here. All other
* directives are handled by the lexer (see lexer.l).
*
*/
#include "verilog_frontend.h"
#include "kernel/log.h"
#include <stdarg.h>
#include <stdio.h>
#include <string.h>
#include <assert.h>
#include <list>
static std::list<std::string> output_code;
static std::list<std::string> input_buffer;
static size_t input_buffer_charp;
static void return_char(char ch)
{
if (input_buffer_charp == 0)
input_buffer.push_front(std::string() + ch);
else
input_buffer.front()[--input_buffer_charp] = ch;
}
static void insert_input(std::string str)
{
if (input_buffer_charp != 0) {
input_buffer.front() = input_buffer.front().substr(input_buffer_charp);
input_buffer_charp = 0;
}
input_buffer.push_front(str);
}
static char next_char()
{
if (input_buffer.size() == 0)
return 0;
assert(input_buffer_charp <= input_buffer.front().size());
if (input_buffer_charp == input_buffer.front().size()) {
input_buffer_charp = 0;
input_buffer.pop_front();
return next_char();
}
char ch = input_buffer.front()[input_buffer_charp++];
return ch == '\r' ? next_char() : ch;
}
static void skip_spaces()
{
while (1) {
char ch = next_char();
if (ch == 0)
break;
if (ch != ' ' && ch != '\t') {
return_char(ch);
break;
}
}
}
static std::string next_token(bool pass_newline = false)
{
std::string token;
char ch = next_char();
if (ch == 0)
return token;
token += ch;
if (ch == '\n') {
if (pass_newline) {
output_code.push_back(token);
return "";
}
return token;
}
if (ch == ' ' || ch == '\t')
{
while ((ch = next_char()) != 0) {
if (ch != ' ' && ch != '\t') {
return_char(ch);
break;
}
token += ch;
}
}
else if (ch == '"')
{
while ((ch = next_char()) != 0) {
token += ch;
if (ch == '"')
break;
if (ch == '\\') {
if ((ch = next_char()) != 0)
token += ch;
}
}
}
else if (ch == '/')
{
if ((ch = next_char()) != 0) {
if (ch == '/') {
token += '*';
char last_ch = 0;
while ((ch = next_char()) != 0) {
if (ch == '\n') {
return_char(ch);
break;
}
if (last_ch != '*' || ch != '/') {
token += ch;
last_ch = ch;
}
}
token += " */";
}
else if (ch == '*') {
token += '*';
int newline_count = 0;
char last_ch = 0;
while ((ch = next_char()) != 0) {
if (ch == '\n') {
newline_count++;
token += ' ';
} else
token += ch;
if (last_ch == '*' && ch == '/')
break;
last_ch = ch;
}
while (newline_count-- > 0)
return_char('\n');
}
else
return_char(ch);
}
}
else
{
const char *ok = "abcdefghijklmnopqrstuvwxyz_ABCDEFGHIJKLMNOPQRSTUVWXYZ$0123456789";
while ((ch = next_char()) != 0) {
if (strchr(ok, ch) == NULL) {
return_char(ch);
break;
}
token += ch;
}
}
return token;
}
static void input_file(FILE *f, std::string filename)
{
char buffer[513];
int rc;
insert_input("");
auto it = input_buffer.begin();
input_buffer.insert(it, "`file_push " + filename + "\n");
while ((rc = fread(buffer, 1, sizeof(buffer)-1, f)) > 0) {
buffer[rc] = 0;
input_buffer.insert(it, buffer);
}
input_buffer.insert(it, "`file_pop\n");
}
static std::string define_to_feature(std::string defname)
{
if (defname == "__YOSYS_ENABLE_DEFATTR__")
return "defattr";
return std::string();
}
std::string frontend_verilog_preproc(FILE *f, std::string filename)
{
std::map<std::string, std::string> defines_map;
int ifdef_fail_level = 0;
output_code.clear();
input_buffer.clear();
input_buffer_charp = 0;
input_file(f, filename);
defines_map["__YOSYS__"] = "1";
while (!input_buffer.empty())
{
std::string tok = next_token();
// printf("token: >>%s<<\n", tok != "\n" ? tok.c_str() : "NEWLINE");
if (tok == "`endif") {
if (ifdef_fail_level > 0)
ifdef_fail_level--;
continue;
}
if (tok == "`else") {
if (ifdef_fail_level == 0)
ifdef_fail_level = 1;
else if (ifdef_fail_level == 1)
ifdef_fail_level = 0;
continue;
}
if (tok == "`ifdef") {
skip_spaces();
std::string name = next_token(true);
if (ifdef_fail_level > 0 || defines_map.count(name) == 0)
ifdef_fail_level++;
continue;
}
if (tok == "`ifndef") {
skip_spaces();
std::string name = next_token(true);
if (ifdef_fail_level > 0 || defines_map.count(name) != 0)
ifdef_fail_level++;
continue;
}
if (ifdef_fail_level > 0) {
if (tok == "\n")
output_code.push_back(tok);
continue;
}
if (tok == "`include") {
skip_spaces();
std::string fn = next_token(true);
while (1) {
size_t pos = fn.find('"');
if (pos == std::string::npos)
break;
if (pos == 0)
fn = fn.substr(1);
else
fn = fn.substr(0, pos) + fn.substr(pos+1);
}
FILE *fp = fopen(fn.c_str(), "r");
if (fp == NULL && fn.size() > 0 && fn[0] != '/' && filename.find('/') != std::string::npos) {
std::string fn2 = filename.substr(0, filename.rfind('/')+1) + fn;
fp = fopen(fn2.c_str(), "r");
}
if (fp != NULL) {
input_file(fp, fn);
fclose(fp);
} else
output_code.push_back("`file_notfound " + fn + "\n");
continue;
}
if (tok == "`define") {
std::string name, value;
skip_spaces();
name = next_token(true);
if (!define_to_feature(name).empty())
output_code.push_back("`yosys_enable_" + define_to_feature(name));
skip_spaces();
int newline_count = 0;
while (!tok.empty()) {
tok = next_token();
if (tok == "\n") {
return_char('\n');
break;
}
if (tok == "\\") {
char ch = next_char();
if (ch == '\n') {
value += " ";
newline_count++;
} else {
value += std::string("\\");
return_char(ch);
}
} else
value += tok;
}
while (newline_count-- > 0)
return_char('\n');
// printf("define: >>%s<< -> >>%s<<\n", name.c_str(), value.c_str());
defines_map[name] = value;
continue;
}
if (tok == "`undef") {
std::string name;
skip_spaces();
name = next_token(true);
if (!define_to_feature(name).empty())
output_code.push_back("`yosys_disable_" + define_to_feature(name));
// printf("undef: >>%s<<\n", name.c_str());
defines_map.erase(name);
continue;
}
if (tok == "`timescale") {
std::string name;
skip_spaces();
while (!tok.empty() && tok != "\n")
tok = next_token(true);
if (tok == "\n")
return_char('\n');
continue;
}
if (tok.size() > 1 && tok[0] == '`' && defines_map.count(tok.substr(1)) > 0) {
// printf("expand: >>%s<< -> >>%s<<\n", tok.c_str(), defines_map[tok.substr(1)].c_str());
insert_input(defines_map[tok.substr(1)]);
continue;
}
output_code.push_back(tok);
}
std::string output;
for (auto &str : output_code)
output += str;
output_code.clear();
input_buffer.clear();
input_buffer_charp = 0;
return output;
}

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* ---
*
* The Verilog frontend.
*
* This frontend is using the AST frontend library (see frontends/ast/).
* Thus this frontend does not generate RTLIL code directly but creates an
* AST directly from the Verilog parse tree and then passes this AST to
* the AST frontend library.
*
*/
#include "verilog_frontend.h"
#include "kernel/register.h"
#include "kernel/log.h"
#include "kernel/sha1.h"
#include <sstream>
#include <stdarg.h>
#include <assert.h>
using namespace VERILOG_FRONTEND;
// use the Verilog bison/flex parser to generate an AST and use AST::process() to convert it to RTLIL
struct VerilogFrontend : public Frontend {
VerilogFrontend() : Frontend("verilog") { }
virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
{
bool flag_dump_ast = false;
bool flag_dump_ast_diff = false;
bool flag_dump_vlog = false;
bool flag_nolatches = false;
bool flag_nomem2reg = false;
bool flag_ppdump = false;
bool flag_nopp = false;
frontend_verilog_yydebug = false;
log_header("Executing Verilog-2005 frontend.\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
std::string arg = args[argidx];
if (arg == "-dump_ast") {
flag_dump_ast = true;
continue;
}
if (arg == "-dump_ast_diff") {
flag_dump_ast = true;
flag_dump_ast_diff = true;
continue;
}
if (arg == "-dump_vlog") {
flag_dump_vlog = true;
continue;
}
if (arg == "-yydebug") {
frontend_verilog_yydebug = true;
continue;
}
if (arg == "-nolatches") {
flag_nolatches = true;
continue;
}
if (arg == "-nomem2reg") {
flag_nomem2reg = true;
continue;
}
if (arg == "-ppdump") {
flag_ppdump = true;
continue;
}
if (arg == "-nopp") {
flag_nopp = true;
continue;
}
break;
}
extra_args(f, filename, args, argidx);
log("Parsing Verilog input from `%s' to AST representation.\n", filename.c_str());
AST::current_filename = filename;
AST::set_line_num = &frontend_verilog_yyset_lineno;
AST::get_line_num = &frontend_verilog_yyget_lineno;
current_ast = new AST::AstNode(AST::AST_DESIGN);
FILE *fp = f;
std::string code_after_preproc;
if (!flag_nopp) {
code_after_preproc = frontend_verilog_preproc(f, filename);
if (flag_ppdump)
log("-- Verilog code after preprocessor --\n%s-- END OF DUMP --\n", code_after_preproc.c_str());
fp = fmemopen((void*)code_after_preproc.c_str(), code_after_preproc.size(), "r");
}
lexer_feature_defattr = false;
frontend_verilog_yyset_lineno(1);
frontend_verilog_yyrestart(fp);
frontend_verilog_yyparse();
frontend_verilog_yylex_destroy();
AST::process(design, current_ast, flag_dump_ast, flag_dump_ast_diff, flag_dump_vlog, flag_nolatches, flag_nomem2reg);
if (!flag_nopp)
fclose(fp);
delete current_ast;
current_ast = NULL;
log("Successfully finished Verilog frontend.\n");
}
} VerilogFrontend;
// the yyerror function used by bison to report parser errors
void frontend_verilog_yyerror(char const *fmt, ...)
{
va_list ap;
char buffer[1024];
char *p = buffer;
p += snprintf(p, buffer + sizeof(buffer) - p, "Parser error in line %s:%d: ",
AST::current_filename.c_str(), frontend_verilog_yyget_lineno());
va_start(ap, fmt);
p += vsnprintf(p, buffer + sizeof(buffer) - p, fmt, ap);
va_end(ap);
p += snprintf(p, buffer + sizeof(buffer) - p, "\n");
log_error("%s", buffer);
exit(1);
}

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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* ---
*
* The Verilog frontend.
*
* This frontend is using the AST frontend library (see frontends/ast/).
* Thus this frontend does not generate RTLIL code directly but creates an
* AST directly from the Verilog parse tree and then passes this AST to
* the AST frontend library.
*
*/
#ifndef VERILOG_FRONTEND_H
#define VERILOG_FRONTEND_H
#include "kernel/rtlil.h"
#include "frontends/ast/ast.h"
#include <stdio.h>
#include <stdint.h>
namespace VERILOG_FRONTEND
{
// this variable is set to a new AST_DESIGN node and then filled with the AST by the bison parser
extern struct AST::AstNode *current_ast;
// this function converts a Verilog constant to an AST_CONSTANT node
AST::AstNode *const2ast(std::string code, char case_type = 0);
// lexer state variables
extern bool lexer_feature_defattr;
}
// the pre-processor
std::string frontend_verilog_preproc(FILE *f, std::string filename);
// the usual bison/flex stuff
extern int frontend_verilog_yydebug;
int frontend_verilog_yylex(void);
void frontend_verilog_yyerror(char const *fmt, ...);
void frontend_verilog_yyrestart(FILE *f);
int frontend_verilog_yyparse(void);
int frontend_verilog_yylex_destroy(void);
int frontend_verilog_yyget_lineno(void);
void frontend_verilog_yyset_lineno (int);
#endif