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Code Activity
yosys/frontends
History
Clifford Wolf 6cc8e848b6 Fixed synthesis of functions in latched blocks
2013-05-16 16:44:06 +02:00
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ast Fixed synthesis of functions in latched blocks 2013-05-16 16:44:06 +02:00
ilang Added help messages to ilang and verilog frontends 2013-03-01 08:03:00 +01:00
verilog Added mem2reg option to verilog frontend 2013-03-24 11:13:32 +01:00