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Tiny fixes to verilog parser

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This commit is contained in:
Clifford Wolf 2013-03-23 18:54:31 +01:00
parent bee57c808a
commit e45d1c8865
2 changed files with 9 additions and 1 deletions
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3
frontends/ast/simplify.cc
View file

@ -120,6 +120,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage)
if (node->type == AST_WIRE) {
if (this_wire_scope.count(node->str) > 0) {
AstNode *first_node = this_wire_scope[node->str];
if (!node->is_input && !node->is_output && node->is_reg && node->children.size() == 0)
goto wires_are_compatible;
if (first_node->children.size() != node->children.size())
goto wires_are_incompatible;
for (size_t j = 0; j < node->children.size(); j++) {
@ -138,6 +140,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage)
goto wires_are_incompatible;
if (first_node->port_id == 0 && (node->is_input || node->is_output))
goto wires_are_incompatible;
wires_are_compatible:
if (node->is_input)
first_node->is_input = true;
if (node->is_output)

7
frontends/verilog/parser.y
View file

@ -209,7 +209,12 @@ module:
};
module_para_opt:
'#' '(' TOK_PARAMETER param_decl_list optional_comma ')' | /* empty */;
'#' '(' module_para_list ')' | /* empty */;
module_para_list:
TOK_PARAMETER single_param_decl |
TOK_PARAMETER single_param_decl ',' module_para_list |
/* empty */;
module_args_opt:
'(' ')' | /* empty */ | '(' module_args optional_comma ')';