mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-06 17:44:09 +00:00
Code Activity

Added support for verilog === operator

Browse source
This commit is contained in:
Clifford Wolf 2013-05-07 14:35:40 +02:00
parent 595db0d7b9
commit b56e06d2f5
1 changed files with 2 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
frontends/verilog/lexer.l
View file

@ -233,6 +233,8 @@ supply1 { return TOK_SUPPLY1; }
"<=" { return OP_LE; }
">=" { return OP_GE; }
"===" { return OP_EQ; }
/* "~&" { return OP_NAND; } */
/* "~|" { return OP_NOR; } */
"~^" { return OP_XNOR; }