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yosys/frontends
History
Clifford Wolf db98a18edb Enabled AST/Verilog front-end optimizations per default
2013-06-10 13:19:04 +02:00
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ast Enabled AST/Verilog front-end optimizations per default 2013-06-10 13:19:04 +02:00
ilang Fixed memory leak in ilang frontend 2013-05-23 12:55:59 +02:00
verilog Enabled AST/Verilog front-end optimizations per default 2013-06-10 13:19:04 +02:00