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Code Activity
17716 commits 138 branches 70 tags 85 MiB
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68 commits

Author SHA1 Message Date
Emil J. Tywoniak
d7c7f69c51 techlibs: fix twines 2026-07-20 13:57:10 +02:00
Emil J. Tywoniak
65f35a88eb WIP migration to twine 2026-07-20 12:27:18 +02:00
Emil J. Tywoniak
b01a3694f0 WIP 2026-07-20 12:27:17 +02:00
Emil J. Tywoniak
77ad54139e WIP 2026-07-20 12:27:17 +02:00
Emil J. Tywoniak
e952044215 WIP 2026-07-20 12:27:17 +02:00
Emil J. Tywoniak
7422b71802 WIP 2026-07-20 12:27:17 +02:00
Emil J. Tywoniak
1210d8e117 WIP 2026-07-20 12:27:02 +02:00
Emil J. Tywoniak
2291084045 pmgen: hold sigmap pointer instead of owning it 2026-07-17 23:38:01 +02:00
Emil J. Tywoniak
cd9b1191f2 signorm: disable in passes that use swap_names 2026-07-17 23:32:34 +02:00
nella
f5809a7c2c
Merge branch 'main' into nella/latch-toggle 2026-07-08 11:41:08 +02:00
nella
362e828dc2 Simplify check -latchonly calls in synth. 2026-07-07 10:10:00 +02:00
nella
a3b8609c84 Add -nolatches check option. 2026-06-24 10:38:10 +02:00
Miodrag Milanovic
a689342207 Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
Miodrag Milanovic
48a3dcc02a End of file fix 2026-06-23 07:23:41 +02:00
nella
b3b1394cf1 Fixup level policy. 2026-06-18 18:00:51 +02:00
nella
32a268d745 Emit errors before dfflegalize. 2026-06-18 17:07:24 +02:00
nella
b2d688dbf9 Error out on latches. 2026-06-17 17:36:32 +02:00
nella
c814ef35e3 Emit latch warning. 2026-06-17 11:27:43 +02:00
Catherine
a727e7f6e7 Migrate build system to CMake 
See #5895 for details.

This commit does not include CI or documentation changes.
 2026-06-03 08:58:10 +00:00
Miodrag Milanovic
4a7878b17f Fixing couple more conversion errors 2026-05-14 15:58:58 +02:00
Codexplorer
e41b969da2 Refactored uses of log_id() 2026-05-08 20:59:24 -07:00
nella
fff034d2f8 Add check before flatten in synth_*. 2026-05-05 14:06:58 +02:00
Lofty
53939bd3ba synth_quicklogic: fix small multiplier inference 2026-03-11 11:14:09 +00:00
Robert O'Callahan
1e5f920dbd Remove .c_str() from parameters to log_debug() 2025-09-23 19:10:33 +12:00
Robert O'Callahan
5ac6858f26 Remove .c_str() from log_cmd_error() and log_file_error() parameters 2025-09-16 22:59:08 +00:00
Robert O'Callahan
1a367b907c Use fast path for 32-bit Const integer constructor in more places 2025-09-16 03:17:24 +00:00
Robert O'Callahan
09b493cfcd Update techlibs to avoid bits() 2025-09-16 03:17:23 +00:00
Robert O'Callahan
c7df6954b9 Remove .c_str() from stringf parameters 2025-09-01 23:34:42 +00:00
N. Engelhardt
15d24bf2e6 synth_quicklogic: add -noflatten option 2025-08-25 17:25:58 +02:00
N. Engelhardt
303a386ecc create duplicate IOFFs if multiple output ports are connected to the same register 2025-01-31 11:28:57 +01:00
N. Engelhardt
25b400982b detect aliased I/O ports 2025-01-28 17:37:23 +01:00
N. Engelhardt
9da4fe747e fix bus ioff inference 2025-01-28 11:23:36 +01:00
N. Engelhardt
1cf8e7c7db add ioff inference for qlf_k6n10f 2025-01-24 21:17:15 +01:00
Emil J. Tywoniak
a58481e9b7 mark all hash_into methods nodiscard 2025-01-14 12:39:15 +01:00
Emil J
9f7040b3d1
Merge pull request #4683 from keszybz/use-SOURCE_DATE_EPOCH 
Respect $SOURCE_DATE_EPOCH in generate_bram_types_sim.py
 2025-01-10 23:43:26 +01:00
Emil J. Tywoniak
b9b9515bb0 hashlib: hash_eat -> hash_into 2024-12-18 15:09:25 +01:00
Emil J. Tywoniak
4e29ec1854 hashlib: acc -> eat 2024-12-18 15:09:25 +01:00
Emil J. Tywoniak
d071489ab1 hashlib: redo interface for flexibility 2024-12-18 14:49:25 +01:00
Krystine Sherwin
1de5d98ae2
Reduce comparisons of size_t and int 
`Const::size()` returns int, so change iterators that use it to `auto` instead of `size_t`.
For cases where size is being explicitly cast to `int`, use the wrapper that we already have instead: `Yosys::GetSize()`.
 2024-11-29 12:53:29 +13:00
Zbigniew Jędrzejewski-Szmek
26a3478d8d Drop timestamp in generate_bram_types_sim.py 
I'm working on build reproducibility of Fedora packages, and this patch fixes
an issue observed in test rebuilds: the timestamp was set to the actual time
of the build, making builds nonreproducible.

Other "Generated by" strings do not include a timestamp, so drop it here too.
 2024-10-30 08:47:18 +01:00
Emil J. Tywoniak
785bd44da7 rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
Martin Povišer
9018d06a33 quicklogic: Avoid carry chains in division mapping 
The default mapping rules for division-like operations (div/divfloor/
mod/modfloor) invoke subtractions which can get mapped to carry chains
in FPGA flows. Optimizations across carry chains are weak, so in
practice this ends up too costly compared to implementing the division
purely in soft logic.

For this reason arrange for `techmap.v` ignoring division operations
under `-D NODIV`, and use this mode in `synth_quicklogic` to avoid carry
chains for divisions.
 2024-09-19 12:18:47 +02:00
Miodrag Milanovic
627fbc3477 Fix Windows build by forcing initialization order, fixes #4068 2024-01-02 11:26:48 +01:00
Miodrag Milanovic
6dc62bd013 Fix out of tree build 2023-12-06 09:56:35 +01:00
Miodrag Milanovic
d71dd5b9bb Fix out of tree build 2023-12-06 09:11:51 +01:00
Martin Povišer
16ea497d7c pmgen: Have a single make pattern 
Remove duplicate %.pmg -> %_pm.h pattern. One of the duplicates overrode
the other, and in some conditions there were build races as to whether
the target directory for the generated header would exist. Instead have
a single rule which is properly generalized.
 2023-12-05 18:30:13 +01:00
Martin Povišer
e0fc48e196 quicklogic: Generate bram_types_sim.v at build time 2023-12-04 18:21:00 +01:00
Martin Povišer
22cc4aff51 quicklogic: Test TDP36K inference with initial data 2023-12-04 15:52:03 +01:00
N. Engelhardt
f9c8978128 add example memory test 2023-12-04 15:52:03 +01:00
Martin Povišer
e0a6a01ecb quicklogic: Add RAM_INIT to specialized BRAM models 2023-12-04 15:52:03 +01:00