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Code Activity
12733 commits 122 branches 59 tags 72 MiB
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3968 commits

Author SHA1 Message Date
Clifford Wolf
64bd414e54 Minor bugfix in "test_pmgen -generate" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-16 14:35:13 +02:00
Clifford Wolf
958be89c47
Merge pull request #1302 from mmicko/dfflibmap_regression 
DFFLIBMAP pass regression fix
 2019-08-16 14:26:58 +02:00
Clifford Wolf
20910fd7c8 Add pmgen finish statement, return number of matches 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-16 14:16:35 +02:00
Clifford Wolf
f45dad8220 Redesign pmgen backtracking for recursive matching 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-16 13:47:50 +02:00
Clifford Wolf
c710df181c Add pmgen "generate" feature 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-16 13:26:36 +02:00
Miodrag Milanovic
72eacdb9f8 Regression in abc9 2019-08-16 13:21:11 +02:00
Miodrag Milanovic
bb79e050a5 Just needed IDs to be IdString 2019-08-16 11:50:34 +02:00
Clifford Wolf
4a57b7e1ab Refactor demo_reduce into test_pmgen 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-16 11:47:51 +02:00
Clifford Wolf
bb37a20e8d Add missing NMUX to "abc -g" handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-16 10:36:11 +02:00
Eddie Hung
eae5a6b12c Use ID::keep more liberally too 2019-08-15 14:51:12 -07:00
Eddie Hung
52355f5185 Use more ID::{A,B,Y,blackbox,whitebox} 2019-08-15 14:50:10 -07:00
Clifford Wolf
016036f247 Add doc for pmgen semioptional statement, Add pmgen changes to CHANGELOG 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-15 23:02:37 +02:00
Clifford Wolf
969ab9027a Update pmgen documentation 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-15 22:48:13 +02:00
Clifford Wolf
eb80d3d43f Change pmgen default rule to reject, switch peepopt behavior to accept 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-15 22:47:59 +02:00
Clifford Wolf
49301b733e
Merge branch 'master' into clifford/fix1255 2019-08-15 22:44:38 +02:00
Eddie Hung
c320abc3f4 xilinx_dsp to be sensitive to keep attribute 2019-08-15 12:34:11 -07:00
Eddie Hung
96ee7b9cf7 Simplify 2019-08-15 12:30:46 -07:00
Eddie Hung
7f10019610 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-15 12:19:51 -07:00
Eddie Hung
27d5df9467 ffH -> ffFJKG 2019-08-15 12:19:34 -07:00
Eddie Hung
6cd8cace0c Fix 2019-08-15 11:25:42 -07:00
Eddie Hung
02dead2e60 ID(\\.*) -> ID(.*) 2019-08-15 10:25:54 -07:00
Eddie Hung
467c34eff0 Convert a few more to ID 2019-08-15 10:24:35 -07:00
Eddie Hung
78ba8b8574 Transform all "\\*" identifiers into ID() 2019-08-15 10:19:29 -07:00
Eddie Hung
9f98241010 Transform "$.*" to ID("$.*") in passes/techmap 2019-08-15 10:05:08 -07:00
Clifford Wolf
03f98d9176 Add demo_reduce pass to demonstrace recursive pattern matching 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-15 18:36:39 +02:00
Clifford Wolf
73bf453929 Improvements in pmgen for recursive patterns 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-15 18:35:56 +02:00
Eddie Hung
4cfefae21e More use of IdString::in() 2019-08-15 09:23:57 -07:00
Eddie Hung
91f6cdfef6 Merge remote-tracking branch 'origin/master' into eddie/fix_1284_again 2019-08-15 06:48:40 -07:00
Clifford Wolf
85b0b2c589
Merge branch 'master' into clifford/ids 2019-08-15 10:22:59 +02:00
Eddie Hung
1551e14d2d AND with an inverted input, causes X{,N}OR output to be inverted too 2019-08-14 16:26:24 -07:00
Eddie Hung
1e47e81869 Revert "Only sort leaves on non-ANDNOT/ORNOT cells" 
This reverts commit 5ec5f6dec7.
 2019-08-14 15:23:25 -07:00
Eddie Hung
5ec5f6dec7 Only sort leaves on non-ANDNOT/ORNOT cells 2019-08-14 11:25:56 -07:00
Eddie Hung
0e128510c0
Revert "Since $_ANDNOT_ is not symmetric, do not sort leaves" 2019-08-14 10:40:53 -07:00
Eddie Hung
aad97168b0 Fixes for reverting SigSpec helper functions 2019-08-14 10:22:33 -07:00
Eddie Hung
2f04beeeb5 Perform C -> PCIN optimisation after pattern matcher 2019-08-13 17:11:35 -07:00
Eddie Hung
1b0e68db94 Revert changes to RTLIL::SigSpec methods 2019-08-13 17:09:28 -07:00
Marcin Kościelnicki
3c75a72feb move attributes to wires 2019-08-13 19:36:59 +00:00
Eddie Hung
0597a3ea23 Rename to XilinxDspPass 2019-08-13 10:23:07 -07:00
Clifford Wolf
0c5db07cd6 Fix various NDEBUG compiler warnings, closes #1255 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-13 13:29:03 +02:00
Marcin Kościelnicki
c6d5b97b98 review fixes 2019-08-13 00:35:54 +00:00
Marcin Kościelnicki
f4c62f33ac Add clock buffer insertion pass, improve iopadmap. 
A few new attributes are defined for use in cell libraries:

- iopad_external_pin: marks PAD cell's external-facing pin.  Pad
  insertion will be skipped for ports that are already connected
  to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
  buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
  Clock buffer insertion will be skipped for nets that are already
  driven by such a pin.

All three are module attributes that should be set to a comma-separeted
list of pin names.

Clock buffer insertion itself works as follows:

1. All cell ports, starting from bottom up, can be marked as clock sinks
   (requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
   buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
   contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
   also connected to a clock sink port in a contained cell, a clock
   buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
   connected to clock sinks, optionally with a special kind of input
   PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
   attribute is set on it.
 2019-08-13 00:16:38 +02:00
Eddie Hung
12c692f6ed Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder" 
This reverts commit c851dc1310, reversing
changes made to f54bf1631f.
 2019-08-12 12:06:45 -07:00
Eddie Hung
f890cfb63b Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-12 11:32:10 -07:00
Eddie Hung
e4a0971581 Since $_ANDNOT_ is not symmetric, do not sort leaves 2019-08-12 11:17:15 -07:00
Eddie Hung
88d5185596 Merge remote-tracking branch 'origin/master' into eddie/fix_1262 2019-08-11 21:13:40 -07:00
Clifford Wolf
6995914f3f Use ID() macro in all of passes/opt/ 
This was obtained by running the following SED command in passes/opt/
and then using "meld foo.cc foo.cc.orig" to manually fix all resulting
compiler errors.

sed -i.orig -r 's/"\\\\([a-zA-Z0-9_]+)"/ID(\1)/g; s/"(\$[a-zA-Z0-9_]+)"/ID(\1)/g;' *.cc

Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-11 11:39:46 +02:00
Eddie Hung
282cc77604 Wrong way around 2019-08-10 11:55:00 -07:00
David Shah
f9020ce2b3
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER" 2019-08-10 17:14:48 +01:00
Eddie Hung
02b0d328ad cover_list -> cover as per @cliffordwolf 2019-08-10 08:26:41 -07:00
Clifford Wolf
f54bf1631f
Merge pull request #1258 from YosysHQ/eddie/cleanup 
Cleanup a few barnacles across codebase
 2019-08-10 09:52:14 +02:00