mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 09:05:32 +00:00
Code Activity

More use of IdString::in()

Browse source
This commit is contained in:
Eddie Hung 2019-08-15 09:23:57 -07:00
parent d8a2aaa463
commit 4cfefae21e
7 changed files with 38 additions and 40 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/cmds/delete.cc
View file

@ -107,7 +107,7 @@ struct DeletePass : public Pass {
for (auto &it : module->cells_) {
if (design->selected(module, it.second))
delete_cells.insert(it.second);
if ((it.second->type == "$memrd" || it.second->type == "$memwr") &&
if (it.second->type.in("$memrd", "$memwr") &&
delete_mems.count(it.second->parameters.at("\\MEMID").decode_string()) != 0)
delete_cells.insert(it.second);
}

2
passes/sat/expose.cc
View file

@ -143,7 +143,7 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::De
continue;
}
if (info.cell->type == "$_DFF_N_" || info.cell->type == "$_DFF_P_") {
if (info.cell->type.in("$_DFF_N_", "$_DFF_P_")) {
info.bit_clk = sigmap(info.cell->getPort("\\C")).as_bit();
info.clk_polarity = info.cell->type == "$_DFF_P_";
info.bit_d = sigmap(info.cell->getPort("\\D")).as_bit();

13
passes/techmap/abc.cc
View file

@ -1043,7 +1043,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
if (builtin_lib)
{
cell_stats[RTLIL::unescape_id(c->type)]++;
if (c->type == "\\ZERO" || c->type == "\\ONE") {
if (c->type.in("\\ZERO", "\\ONE")) {
RTLIL::SigSig conn;
conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]);
conn.second = RTLIL::SigSpec(c->type == "\\ZERO" ? 0 : 1, 1);
@ -1065,8 +1065,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
design->select(module, cell);
continue;
}
if (c->type == "\\AND" || c->type == "\\OR" || c->type == "\\XOR" || c->type == "\\NAND" || c->type == "\\NOR" ||
c->type == "\\XNOR" || c->type == "\\ANDNOT" || c->type == "\\ORNOT") {
if (c->type.in("\\AND", "\\OR", "\\XOR", "\\NAND", "\\NOR", "\\XNOR", "\\ANDNOT", "\\ORNOT")) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_");
if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
@ -1075,7 +1074,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
design->select(module, cell);
continue;
}
if (c->type == "\\MUX" || c->type == "\\NMUX") {
if (c->type.in("\\MUX", "\\NMUX")) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_");
if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
@ -1143,7 +1142,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
design->select(module, cell);
continue;
}
if (c->type == "\\AOI3" || c->type == "\\OAI3") {
if (c->type.in("\\AOI3", "\\OAI3")) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_");
if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
@ -1153,7 +1152,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
design->select(module, cell);
continue;
}
if (c->type == "\\AOI4" || c->type == "\\OAI4") {
if (c->type.in("\\AOI4", "\\OAI4")) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_");
if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
@ -1185,7 +1184,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
else
cell_stats[RTLIL::unescape_id(c->type)]++;
if (c->type == "\\_const0_" || c->type == "\\_const1_") {
if (c->type.in("\\_const0_", "\\_const1_")) {
RTLIL::SigSig conn;
conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->connections().begin()->second.as_wire()->name)]);
conn.second = RTLIL::SigSpec(c->type == "\\_const0_" ? 0 : 1, 1);

2
passes/techmap/shregmap.cc
View file

@ -130,7 +130,7 @@ struct ShregmapTechXilinx7 : ShregmapTech
if (cell) {
if (cell->type == "$shiftx" && port == "\\A")
return;
if (cell->type == "$mux" && (port == "\\A" || port == "\\B"))
if (cell->type == "$mux" && port.in("\\A", "\\B"))
return;
}
sigbit_to_shiftx_offset.erase(it);

4
passes/techmap/techmap.cc
View file

@ -349,7 +349,7 @@ struct TechmapWorker
port_signal_map.apply(it2.second);
}
if (c->type == "$memrd" || c->type == "$memwr" || c->type == "$meminit") {
if (c->type.in("$memrd", "$memwr", "$meminit")) {
IdString memid = c->getParam("\\MEMID").decode_string();
log_assert(memory_renames.count(memid) != 0);
c->setParam("\\MEMID", Const(memory_renames[memid].str()));
@ -520,7 +520,7 @@ struct TechmapWorker
int port_counter = 1;
for (auto &c : extmapper_cell->connections_) {
RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second));
if (w->name == "\\Y" || w->name == "\\Q")
if (w->name.in("\\Y", "\\Q"))
w->port_output = true;
else
w->port_input = true;

4
passes/tests/test_cell.cc
View file

@ -43,7 +43,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
RTLIL::Cell *cell = module->addCell("\\UUT", cell_type);
RTLIL::Wire *wire;
if (cell_type == "$mux" || cell_type == "$pmux")
if (cell_type.in("$mux", "$pmux"))
{
int width = 1 + xorshift32(8);
int swidth = cell_type == "$mux" ? 1 : 1 + xorshift32(8);
@ -264,7 +264,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
cell->setPort("\\Y", wire);
}
if (muxdiv && (cell_type == "$div" || cell_type == "$mod")) {
if (muxdiv && cell_type.in("$div", "$mod")) {
auto b_not_zero = module->ReduceBool(NEW_ID, cell->getPort("\\B"));
auto div_out = module->addWire(NEW_ID, GetSize(cell->getPort("\\Y")));
module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(div_out)), div_out, b_not_zero, cell->getPort("\\Y"));