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https://github.com/YosysHQ/yosys
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Add clock buffer insertion pass, improve iopadmap.
A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it.
This commit is contained in:
Marcin Kościelnicki
parent
78b30bbb11
commit
f4c62f33ac
10 changed files with 577 additions and 93 deletions
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@ -16,6 +16,7 @@ endif
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ifneq ($(SMALL),1)
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OBJS += passes/techmap/iopadmap.o
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OBJS += passes/techmap/clkbufmap.o
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OBJS += passes/techmap/hilomap.o
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OBJS += passes/techmap/extract.o
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OBJS += passes/techmap/extract_fa.o
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299
passes/techmap/clkbufmap.cc
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299
passes/techmap/clkbufmap.cc
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@ -0,0 +1,299 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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void split_portname_pair(std::string &port1, std::string &port2)
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{
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size_t pos = port1.find_first_of(':');
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if (pos != std::string::npos) {
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port2 = port1.substr(pos+1);
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port1 = port1.substr(0, pos);
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}
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}
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std::vector<std::string> split(std::string text, const char *delim)
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{
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std::vector<std::string> list;
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char *p = strdup(text.c_str());
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char *t = strtok(p, delim);
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while (t != NULL) {
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list.push_back(t);
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t = strtok(NULL, delim);
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}
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free(p);
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return list;
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}
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struct ClkbufmapPass : public Pass {
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ClkbufmapPass() : Pass("clkbufmap", "insert global buffers on clock networks") { }
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void help() YS_OVERRIDE
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{
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log("\n");
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log(" clkbufmap [options] [selection]\n");
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log("\n");
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log("Inserts global buffers between nets connected to clock inputs and their\n");
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log("drivers.\n");
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log("\n");
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log(" -buf <celltype> <portname_out>:<portname_in>\n");
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log(" Specifies the cell type to use for the global buffers\n");
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log(" and its port names. The first port will be connected to\n");
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log(" the clock network sinks, and the second will be connected\n");
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log(" to the actual clock source. This option is required.\n");
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log("\n");
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log(" -inpad <celltype> <portname_out>:<portname_in>\n");
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log(" If specified, a PAD cell of the given type is inserted on\n");
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log(" clock nets that are also top module's inputs (in addition\n");
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log(" to the global buffer).\n");
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log("\n");
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}
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void module_queue(Design *design, Module *module, std::vector<Module *> &modules_sorted, pool<Module *> &modules_processed) {
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if (modules_processed.count(module))
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return;
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for (auto cell : module->cells()) {
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Module *submodule = design->module(cell->type);
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if (!submodule)
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continue;
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module_queue(design, submodule, modules_sorted, modules_processed);
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}
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modules_sorted.push_back(module);
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modules_processed.insert(module);
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing CLKBUFMAP pass (inserting global clock buffers).\n");
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std::string buf_celltype, buf_portname, buf_portname2;
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std::string inpad_celltype, inpad_portname, inpad_portname2;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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std::string arg = args[argidx];
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if (arg == "-buf" && argidx+2 < args.size()) {
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buf_celltype = args[++argidx];
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buf_portname = args[++argidx];
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split_portname_pair(buf_portname, buf_portname2);
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continue;
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}
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if (arg == "-inpad" && argidx+2 < args.size()) {
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inpad_celltype = args[++argidx];
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inpad_portname = args[++argidx];
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split_portname_pair(inpad_portname, inpad_portname2);
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (buf_celltype.empty())
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log_error("The -buf option is required.");
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// Cell type, port name, bit index.
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pool<pair<IdString, pair<IdString, int>>> sink_ports;
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pool<pair<IdString, pair<IdString, int>>> buf_ports;
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// Process submodules before module using them.
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std::vector<Module *> modules_sorted;
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pool<Module *> modules_processed;
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for (auto module : design->selected_modules())
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module_queue(design, module, modules_sorted, modules_processed);
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for (auto module : modules_sorted)
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{
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if (module->get_blackbox_attribute()) {
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auto it = module->attributes.find("\\clkbuf_driver");
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if (it != module->attributes.end()) {
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auto value = it->second.decode_string();
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for (auto name : split(value, ",")) {
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auto wire = module->wire(RTLIL::escape_id(name));
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if (!wire)
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log_error("Module %s does not have port %s.\n", log_id(module), log_id(name));
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for (int i = 0; i < GetSize(wire); i++)
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buf_ports.insert(make_pair(module->name, make_pair(RTLIL::escape_id(name), i)));
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}
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}
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it = module->attributes.find("\\clkbuf_sink");
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if (it != module->attributes.end()) {
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auto value = it->second.decode_string();
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for (auto name : split(value, ",")) {
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auto wire = module->wire(RTLIL::escape_id(name));
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if (!wire)
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log_error("Module %s does not have port %s.\n", log_id(module), log_id(name));
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for (int i = 0; i < GetSize(wire); i++)
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sink_ports.insert(make_pair(module->name, make_pair(RTLIL::escape_id(name), i)));
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}
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}
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continue;
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}
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pool<SigBit> sink_wire_bits;
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pool<SigBit> buf_wire_bits;
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pool<SigBit> driven_wire_bits;
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SigMap sigmap(module);
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// bit -> (buffer, buffer's input)
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dict<SigBit, pair<Cell *, Wire *>> buffered_bits;
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// First, collect nets that could use a clock buffer.
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for (auto cell : module->cells())
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for (auto port : cell->connections())
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for (int i = 0; i < port.second.size(); i++)
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if (sink_ports.count(make_pair(cell->type, make_pair(port.first, i))))
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sink_wire_bits.insert(sigmap(port.second[i]));
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// Second, collect ones that already have a clock buffer.
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for (auto cell : module->cells())
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for (auto port : cell->connections())
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for (int i = 0; i < port.second.size(); i++)
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if (buf_ports.count(make_pair(cell->type, make_pair(port.first, i))))
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buf_wire_bits.insert(sigmap(port.second[i]));
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// Collect all driven bits.
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for (auto cell : module->cells())
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for (auto port : cell->connections())
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if (cell->output(port.first))
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for (int i = 0; i < port.second.size(); i++)
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driven_wire_bits.insert(port.second[i]);
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// Insert buffers.
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std::vector<pair<Wire *, Wire *>> input_queue;
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for (auto wire : module->selected_wires())
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{
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// Should not happen.
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if (wire->port_input && wire->port_output)
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continue;
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if (wire->get_bool_attribute("\\clkbuf_inhibit"))
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continue;
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pool<int> input_bits;
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for (int i = 0; i < GetSize(wire); i++)
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{
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SigBit wire_bit(wire, i);
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SigBit mapped_wire_bit = sigmap(wire_bit);
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if (buf_wire_bits.count(mapped_wire_bit)) {
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// Already buffered downstream. If this is an output, mark it.
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if (wire->port_output)
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buf_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
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} else if (!sink_wire_bits.count(mapped_wire_bit)) {
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// Nothing to do.
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} else if (driven_wire_bits.count(wire_bit) || (wire->port_input && module->get_bool_attribute("\\top"))) {
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// Clock network not yet buffered, driven by one of
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// our cells or a top-level input -- buffer it.
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log("Inserting %s on %s.%s[%d].\n", buf_celltype.c_str(), log_id(module), log_id(wire), i);
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RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(buf_celltype));
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Wire *iwire = module->addWire(NEW_ID);
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cell->setPort(RTLIL::escape_id(buf_portname), mapped_wire_bit);
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cell->setPort(RTLIL::escape_id(buf_portname2), iwire);
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if (wire->port_input && !inpad_celltype.empty() && module->get_bool_attribute("\\top")) {
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log("Inserting %s on %s.%s[%d].\n", inpad_celltype.c_str(), log_id(module), log_id(wire), i);
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RTLIL::Cell *cell2 = module->addCell(NEW_ID, RTLIL::escape_id(inpad_celltype));
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cell2->setPort(RTLIL::escape_id(inpad_portname), iwire);
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iwire = module->addWire(NEW_ID);
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cell2->setPort(RTLIL::escape_id(inpad_portname2), iwire);
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}
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buffered_bits[mapped_wire_bit] = make_pair(cell, iwire);
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if (wire->port_input) {
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input_bits.insert(i);
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}
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} else if (wire->port_input) {
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// A clock input in a submodule -- mark it, let higher level
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// worry about it.
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if (wire->port_input)
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sink_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
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}
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}
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if (!input_bits.empty()) {
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// This is an input port and some buffers were inserted -- we need
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// to create a new input wire and transfer attributes.
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Wire *new_wire = module->addWire(NEW_ID, wire);
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for (int i = 0; i < wire->width; i++) {
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SigBit wire_bit(wire, i);
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SigBit mapped_wire_bit = sigmap(wire_bit);
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auto it = buffered_bits.find(mapped_wire_bit);
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if (it != buffered_bits.end()) {
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module->connect(it->second.second, SigSpec(new_wire, i));
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} else {
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module->connect(SigSpec(wire, i), SigSpec(new_wire, i));
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}
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}
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input_queue.push_back(make_pair(wire, new_wire));
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}
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}
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// Mark any newly-buffered output ports as such.
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for (auto wire : module->selected_wires()) {
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if (wire->port_input || !wire->port_output)
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continue;
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for (int i = 0; i < GetSize(wire); i++)
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{
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SigBit wire_bit(wire, i);
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SigBit mapped_wire_bit = sigmap(wire_bit);
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if (buffered_bits.count(mapped_wire_bit))
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buf_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
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}
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}
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// Reconnect the drivers to buffer inputs.
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for (auto cell : module->cells())
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for (auto port : cell->connections()) {
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if (!cell->output(port.first))
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continue;
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SigSpec sig = port.second;
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bool newsig = false;
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for (auto &bit : sig) {
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const auto it = buffered_bits.find(sigmap(bit));
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if (it == buffered_bits.end())
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continue;
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// Avoid substituting buffer's own output pin.
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if (cell == it->second.first)
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continue;
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bit = it->second.second;
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newsig = true;
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}
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if (newsig)
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cell->setPort(port.first, sig);
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}
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// This has to be done last, to avoid upsetting sigmap before the port reconnections.
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for (auto &it : input_queue) {
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Wire *wire = it.first;
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Wire *new_wire = it.second;
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module->swap_names(new_wire, wire);
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wire->attributes.clear();
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wire->port_id = 0;
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wire->port_input = false;
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wire->port_output = false;
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}
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module->fixup_ports();
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}
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}
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} ClkbufmapPass;
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PRIVATE_NAMESPACE_END
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@ -32,6 +32,19 @@ void split_portname_pair(std::string &port1, std::string &port2)
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}
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}
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std::vector<std::string> split(std::string text, const char *delim)
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{
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std::vector<std::string> list;
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char *p = strdup(text.c_str());
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char *t = strtok(p, delim);
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while (t != NULL) {
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list.push_back(t);
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t = strtok(NULL, delim);
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}
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free(p);
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return list;
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}
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struct IopadmapPass : public Pass {
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IopadmapPass() : Pass("iopadmap", "technology mapping of i/o pads (or buffers)") { }
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void help() YS_OVERRIDE
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@ -64,6 +77,11 @@ struct IopadmapPass : public Pass {
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log(" of the tristate driver and the 2nd portname is the internal output\n");
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log(" buffering the external signal.\n");
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log("\n");
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log(" -ignore <celltype> <portname>[:<portname>]*\n");
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log(" Skips mapping inputs/outputs that are already connected to given\n");
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log(" ports of the given cell. Can be used multiple times. This is in\n");
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log(" addition to the cells specified as mapping targets.\n");
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log("\n");
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log(" -widthparam <param_name>\n");
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log(" Use the specified parameter name to set the port width.\n");
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log("\n");
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@ -88,6 +106,7 @@ struct IopadmapPass : public Pass {
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std::string toutpad_celltype, toutpad_portname, toutpad_portname2, toutpad_portname3;
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std::string tinoutpad_celltype, tinoutpad_portname, tinoutpad_portname2, tinoutpad_portname3, tinoutpad_portname4;
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std::string widthparam, nameparam;
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pool<pair<IdString, IdString>> ignore;
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bool flag_bits = false;
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size_t argidx;
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@ -127,6 +146,18 @@ struct IopadmapPass : public Pass {
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split_portname_pair(tinoutpad_portname3, tinoutpad_portname4);
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continue;
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}
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if (arg == "-ignore" && argidx+2 < args.size()) {
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std::string ignore_celltype = args[++argidx];
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std::string ignore_portname = args[++argidx];
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std::string ignore_portname2;
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while (!ignore_portname.empty()) {
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split_portname_pair(ignore_portname, ignore_portname2);
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ignore.insert(make_pair(RTLIL::escape_id(ignore_celltype), RTLIL::escape_id(ignore_portname)));
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ignore_portname = ignore_portname2;
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}
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continue;
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}
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if (arg == "-widthparam" && argidx+1 < args.size()) {
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widthparam = args[++argidx];
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continue;
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@ -143,6 +174,28 @@ struct IopadmapPass : public Pass {
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}
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extra_args(args, argidx, design);
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if (!inpad_portname2.empty())
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ignore.insert(make_pair(RTLIL::escape_id(inpad_celltype), RTLIL::escape_id(inpad_portname2)));
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if (!outpad_portname2.empty())
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ignore.insert(make_pair(RTLIL::escape_id(outpad_celltype), RTLIL::escape_id(outpad_portname2)));
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if (!inoutpad_portname2.empty())
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ignore.insert(make_pair(RTLIL::escape_id(inoutpad_celltype), RTLIL::escape_id(inoutpad_portname2)));
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if (!toutpad_portname3.empty())
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ignore.insert(make_pair(RTLIL::escape_id(toutpad_celltype), RTLIL::escape_id(toutpad_portname3)));
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if (!tinoutpad_portname4.empty())
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ignore.insert(make_pair(RTLIL::escape_id(tinoutpad_celltype), RTLIL::escape_id(tinoutpad_portname4)));
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for (auto module : design->modules())
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{
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auto it = module->attributes.find("\\iopad_external_pin");
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if (it != module->attributes.end()) {
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auto value = it->second.decode_string();
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for (auto name : split(value, ",")) {
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ignore.insert(make_pair(module->name, RTLIL::escape_id(name)));
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}
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}
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}
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for (auto module : design->selected_modules())
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{
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dict<IdString, pool<int>> skip_wires;
|
||||
|
|
@ -150,28 +203,11 @@ struct IopadmapPass : public Pass {
|
|||
SigMap sigmap(module);
|
||||
|
||||
for (auto cell : module->cells())
|
||||
{
|
||||
if (cell->type == RTLIL::escape_id(inpad_celltype) && cell->hasPort(RTLIL::escape_id(inpad_portname2)))
|
||||
for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(inpad_portname2))))
|
||||
for (auto port : cell->connections())
|
||||
if (ignore.count(make_pair(cell->type, port.first)))
|
||||
for (auto bit : sigmap(port.second))
|
||||
skip_wire_bits.insert(bit);
|
||||
|
||||
if (cell->type == RTLIL::escape_id(outpad_celltype) && cell->hasPort(RTLIL::escape_id(outpad_portname2)))
|
||||
for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(outpad_portname2))))
|
||||
skip_wire_bits.insert(bit);
|
||||
|
||||
if (cell->type == RTLIL::escape_id(inoutpad_celltype) && cell->hasPort(RTLIL::escape_id(inoutpad_portname2)))
|
||||
for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(inoutpad_portname2))))
|
||||
skip_wire_bits.insert(bit);
|
||||
|
||||
if (cell->type == RTLIL::escape_id(toutpad_celltype) && cell->hasPort(RTLIL::escape_id(toutpad_portname3)))
|
||||
for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(toutpad_portname3))))
|
||||
skip_wire_bits.insert(bit);
|
||||
|
||||
if (cell->type == RTLIL::escape_id(tinoutpad_celltype) && cell->hasPort(RTLIL::escape_id(tinoutpad_portname4)))
|
||||
for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(tinoutpad_portname4))))
|
||||
skip_wire_bits.insert(bit);
|
||||
}
|
||||
|
||||
if (!toutpad_celltype.empty() || !tinoutpad_celltype.empty())
|
||||
{
|
||||
dict<SigBit, pair<IdString, pool<IdString>>> tbuf_bits;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue