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yosys/passes
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Clifford Wolf 85b0b2c589
Merge branch 'master' into clifford/ids
2019-08-15 10:22:59 +02:00
..
cmds substr() -> compare() 2019-08-07 12:20:08 -07:00
equiv substr() -> compare() 2019-08-07 12:20:08 -07:00
fsm RTLIL::S{0,1} -> State::S{0,1} 2019-08-07 11:12:38 -07:00
hierarchy stoi -> atoi 2019-08-07 11:09:17 -07:00
memory stoi -> atoi 2019-08-07 11:09:17 -07:00
opt Merge branch 'master' into clifford/ids 2019-08-15 10:22:59 +02:00
pmgen Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER" 2019-08-10 17:14:48 +01:00
proc Merge pull request #1258 from YosysHQ/eddie/cleanup 2019-08-10 09:52:14 +02:00
sat substr() -> compare() 2019-08-07 12:20:08 -07:00
techmap Revert "Since $_ANDNOT_ is not symmetric, do not sort leaves" 2019-08-14 10:40:53 -07:00
tests substr() -> compare() 2019-08-07 12:20:08 -07:00