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yosys/passes
2019-08-15 12:30:46 -07:00
..
cmds substr() -> compare() 2019-08-07 12:20:08 -07:00
equiv substr() -> compare() 2019-08-07 12:20:08 -07:00
fsm RTLIL::S{0,1} -> State::S{0,1} 2019-08-07 11:12:38 -07:00
hierarchy stoi -> atoi 2019-08-07 11:09:17 -07:00
memory stoi -> atoi 2019-08-07 11:09:17 -07:00
opt Merge branch 'master' into clifford/ids 2019-08-15 10:22:59 +02:00
pmgen Simplify 2019-08-15 12:30:46 -07:00
proc Merge pull request #1258 from YosysHQ/eddie/cleanup 2019-08-10 09:52:14 +02:00
sat substr() -> compare() 2019-08-07 12:20:08 -07:00
techmap AND with an inverted input, causes X{,N}OR output to be inverted too 2019-08-14 16:26:24 -07:00
tests Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-12 11:32:10 -07:00