1458 commits

Author	SHA1	Message	Date
Clifford Wolf	10e5791c5e	Refactoring: Renamed RTLIL::Design::modules to modules_	2014-07-27 11:18:30 +02:00
Clifford Wolf	4c4b602156	Refactoring: Renamed RTLIL::Module::cells to cells_	2014-07-27 01:51:45 +02:00
Clifford Wolf	f9946232ad	Refactoring: Renamed RTLIL::Module::wires to wires_	2014-07-27 01:49:51 +02:00
Clifford Wolf	946ddff9ce	Changed a lot of code to the new RTLIL::Wire constructors	2014-07-26 20:12:50 +02:00
Clifford Wolf	97a59851a6	Added RTLIL::Cell::has(portname)	2014-07-26 16:11:28 +02:00
Clifford Wolf	f8fdc47d33	Manual fixes for new cell connections API	2014-07-26 15:58:23 +02:00
Clifford Wolf	b7dda72302	Changed users of cell->connections_ to the new API (sed command) ... git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'	2014-07-26 15:58:23 +02:00
Clifford Wolf	cc4f10883b	Renamed RTLIL::{Module,Cell}::connections to connections_	2014-07-26 11:58:03 +02:00
Clifford Wolf	2bec47a404	Use only module->addCell() and module->remove() to create and delete cells	2014-07-25 17:56:19 +02:00
Clifford Wolf	309d64d46a	Fixed two memory leaks in ast simplify	2014-07-25 13:24:10 +02:00
Clifford Wolf	1488bc0c4f	Updated verific build/test instructions	2014-07-25 12:16:03 +02:00
Clifford Wolf	6aa792c864	Replaced more old SigChunk programming patterns	2014-07-24 23:10:58 +02:00
Clifford Wolf	b17d6531c8	Added "make PRETTY=1"	2014-07-24 17:15:01 +02:00
Clifford Wolf	375aa71dfe	Various fixes in Verific frontend for new RTLIL API	2014-07-23 21:35:01 +02:00
Clifford Wolf	20a7965f61	Various small fixes (from gcc compiler warnings)	2014-07-23 20:45:27 +02:00
Clifford Wolf	c094c53de8	Removed RTLIL::SigSpec::optimize()	2014-07-23 20:32:28 +02:00
Clifford Wolf	ec923652e2	Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	2014-07-23 09:52:55 +02:00
Clifford Wolf	a8d3a68971	Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	2014-07-23 09:49:43 +02:00
Clifford Wolf	115dd959d9	SigSpec refactoring: More cleanups of old SigSpec use pattern	2014-07-22 23:50:21 +02:00
Clifford Wolf	28b3fd05fa	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()	2014-07-22 20:58:44 +02:00
Clifford Wolf	7bffde6abd	SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only	2014-07-22 20:39:38 +02:00
Clifford Wolf	4b4048bc5f	SigSpec refactoring: using the accessor functions everywhere	2014-07-22 20:39:37 +02:00
Clifford Wolf	a233762a81	SigSpec refactoring: renamed chunks and width to __chunks and __width	2014-07-22 20:39:37 +02:00
Clifford Wolf	3b5f4ff39c	Fixed ilang parsing of process attributes	2014-07-22 20:39:37 +02:00
Clifford Wolf	d6d0e08834	Fixed make rules for ilang parser	2014-07-22 20:39:37 +02:00
Clifford Wolf	4147b55c23	Added "autoidx" statement to ilang file format	2014-07-21 15:15:18 +02:00
Clifford Wolf	361e0d62ff	Replaced depricated NEW_WIRE macro with module->addWire() calls	2014-07-21 12:42:02 +02:00
Clifford Wolf	1d88f1cf9f	Removed deprecated module->new_wire()	2014-07-21 12:35:06 +02:00
Clifford Wolf	9b183539af	Implemented dynamic bit-/part-select for memory writes	2014-07-17 16:49:23 +02:00
Clifford Wolf	5867f6bcdc	Added support for bit/part select to mem2reg rewriter	2014-07-17 13:49:32 +02:00
Clifford Wolf	6d69d4aaa8	Added support for constant bit- or part-select for memory writes	2014-07-17 13:13:21 +02:00
Clifford Wolf	b171a4c1bc	Added "inout" ports support to read_liberty	2014-07-16 18:12:46 +02:00
Clifford Wolf	5057935722	Set blackbox attribute in "read_liberty -lib"	2014-07-16 18:12:16 +02:00
Clifford Wolf	24f58e57f3	Fixed spelling of "direction" in read_liberty messages	2014-07-16 18:02:28 +02:00
Clifford Wolf	543551b80a	changes in verilog frontend for new $mem/$memwr WR_EN interface	2014-07-16 12:49:50 +02:00
Clifford Wolf	0f9ca49dc6	Added passing of various options to vhdl2verilog	2014-07-12 10:02:39 +02:00
Clifford Wolf	55a1b8dbac	Fixed processing of initial values for block-local variables	2014-07-11 13:05:53 +02:00
Clifford Wolf	ee8ad72fd9	fixed parsing of constant with comment between size and value	2014-07-02 06:27:04 +02:00
Clifford Wolf	076182c34e	Fixed handling of mixed real/int ternary expressions	2014-06-25 10:05:36 +02:00
Clifford Wolf	4fc43d1932	More found_real-related fixes to AstNode::detectSignWidthWorker	2014-06-24 15:08:48 +02:00
Clifford Wolf	65b2e9c064	fixed signdness detection for expressions with reals	2014-06-21 21:41:13 +02:00
Clifford Wolf	80e4594695	Added AstNode::MEM2REG_FL_CMPLX_LHS	2014-06-17 21:39:25 +02:00
Clifford Wolf	798ff88855	Improved handling of relational op of real values	2014-06-17 12:47:51 +02:00
Clifford Wolf	6c17d4f242	Improved ternary support for real values	2014-06-16 15:12:24 +02:00
Clifford Wolf	82bbd2f077	Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012	2014-06-16 15:05:37 +02:00
Clifford Wolf	0c4c79c4c6	Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)	2014-06-16 15:02:40 +02:00
Clifford Wolf	5bfe865cec	Added found_real feature to AstNode::detectSignWidth	2014-06-16 15:00:57 +02:00
Clifford Wolf	4d1df128fa	Improved AstNode::realAsConst for large numbers	2014-06-15 09:27:09 +02:00
Clifford Wolf	7f57bc8385	Improved parsing of large integer constants	2014-06-15 08:48:17 +02:00
Clifford Wolf	48dc6ab98d	Improved AstNode::asReal for large integers	2014-06-15 08:38:31 +02:00