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Code Activity
13772 commits 122 branches 59 tags 72 MiB
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1436 commits

Author SHA1 Message Date
Marcelina Kościelnicka
516857f3ba [NFCI] Deduplicate builtin FF cell types list 
A few passes included the same list of FF cell types.  Make it a global
const instead.

The zinit pass also seems to include a list like that, but given that
it seems to be completely broken at the time (see #1568 discussion),
I'm going to pretend I didn't see that.
 2020-04-09 18:05:06 +02:00
whitequark
d20e971725 write_cxxrtl: new backend. 
This commit adds a basic implementation that isn't very performant
but implements most of the planned features.
 2020-04-09 04:08:36 +00:00
Alberto Gonzalez
a4598d64ef
Hole value recovery and specialization implementation for qbfsat command. 2020-04-04 22:13:25 +00:00
Eddie Hung
956ecd48f7 kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
Eddie Hung
2d86563bb2 kernel: IdString::in(const IdString &) as per @Tjoppen 2020-04-02 07:14:08 -07:00
Eddie Hung
18d85b88ae kernel: fix formatting (thanks @boqwxp) 2020-04-02 07:14:08 -07:00
Eddie Hung
7bcbf0c9d1 kernel: use C++11 fold hack to prevent recursion 2020-04-02 07:14:08 -07:00
Eddie Hung
ba13a40ef4 Revert "kernel: IdString:in() to use perfect forwarding" 
This reverts commit 7b2a85aedf24affc2e1202c78e70e6a317f5bf29.
 2020-04-02 07:14:08 -07:00
Eddie Hung
6d4f01c3fa kernel: separate IdString::put_reference() out to help inlining 2020-04-02 07:14:08 -07:00
Eddie Hung
4a8cecf03e kernel: IdString:in() to use perfect forwarding 2020-04-02 07:14:08 -07:00
Eddie Hung
164dd0f6b2 kernel: Use constids.inc for global/constant IdStrings 2020-04-02 07:14:08 -07:00
Eddie Hung
37f42fe102
Merge pull request #1845 from YosysHQ/eddie/kernel_speedup 
kernel: speedup by using more pass-by-const-ref
 2020-04-02 07:13:33 -07:00
Eddie Hung
c90324662c
Merge pull request #1828 from YosysHQ/eddie/celltypes_speedup 
kernel: share a single CellTypes within a pass
 2020-04-01 14:17:45 -07:00
Alberto Gonzalez
ae05795f54
Clean up pseudo-private member usage in kernel/yosys.cc. 2020-04-01 02:53:56 +00:00
Eddie Hung
348e892314 kernel: pass-by-value into Design::scratchpad_set_string() too 2020-03-27 12:21:09 -07:00
Rupert Swarbrick
044ca9dde4 Add support for SystemVerilog-style `define to Verilog frontend 
This patch should support things like

  `define foo(a, b = 3, c)   a+b+c

  `foo(1, ,2)

which will evaluate to 1+3+2. It also spots mistakes like

  `foo(1)

(the 3rd argument doesn't have a default value, so a call site is
required to set it).

Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.

Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.

Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.
 2020-03-27 16:08:26 +00:00
Eddie Hung
6ca7844cec kernel: const Wire* overload -> Wire* !!! 2020-03-26 16:21:30 -07:00
Eddie Hung
f97b90e40b kernel: Cell::set{Port,Param}() to pass by value, but use std::move 
Otherwise cell->setPort(ID::A, cell->getPort(ID::B)) could be invalid
 2020-03-26 14:33:06 -07:00
Eddie Hung
7ad7f41bc5 kernel: share a single CellTypes within a pass 2020-03-18 12:21:40 -07:00
Eddie Hung
940640ac44 kernel: SigSpec copies to not trigger pack() 2020-03-18 11:51:00 -07:00
Eddie Hung
4555b5b819 kernel: more pass by const ref, more speedups 2020-03-18 11:21:53 -07:00
Eddie Hung
8b12e97153 kernel: speedup 2020-03-18 08:48:36 -07:00
Eddie Hung
8c45ea9f0e kernel: use const reference for SigSet too 2020-03-17 10:22:33 -07:00
Eddie Hung
bc51e609cb kernel: fix DeleteWireWorker 2020-03-17 10:22:16 -07:00
Claire Wolf
ed4fa19ba2 Update Copyright 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-03-16 16:28:25 +01:00
Waldir Pimenta
418c069561 License: bump year and add title 2020-03-14 16:46:07 +00:00
Miodrag Milanovic
395daf6ced exclude clang from checking 2020-03-13 17:23:27 +01:00
Miodrag Milanovic
8f221118d2 Add YS_ prefix to macros, add explanation and apply to older version as well 2020-03-13 17:19:54 +01:00
Eddie Hung
432a09af80 kernel: SigSpec use more const& + overloads to prevent implicit SigSpec 2020-03-13 08:17:39 -07:00
Miodrag Milanovic
7c54e61979 Use boost xpressive for gcc 4.8 2020-03-13 14:58:35 +01:00
Eddie Hung
b567f03c26 kernel: optimise Module::remove(const pool<RTLIL::Wire*>() 2020-03-12 16:00:34 -07:00
Eddie Hung
a076052fe4 kernel: SigPool to use const& + overloads to prevent implicit SigSpec 2020-03-12 16:00:34 -07:00
jiegec
7b679eecb3 Fix compilation for emcc 2020-03-11 22:09:24 +08:00
David Shah
b8abf14376 Add ScriptPass::run_nocheck and use for abc9 
Signed-off-by: David Shah <dave@ds0.me>
 2020-03-09 14:34:22 +00:00
Claire Wolf
b597f85b13
Merge pull request #1718 from boqwxp/precise_locations 
Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
 2020-03-03 08:38:32 -08:00
Eddie Hung
0f4c1906bb Small fixes 2020-02-27 10:29:53 -08:00
Eddie Hung
78929e8c3d Fixes for older compilers 2020-02-27 10:17:29 -08:00
Eddie Hung
6bb3d9f9c0 Make TimingInfo::TimingInfo(SigBit) constructor explicit 2020-02-27 10:17:29 -08:00
Eddie Hung
9dcf204dec TimingInfo: index by (port_name,offset) 2020-02-27 10:17:29 -08:00
Eddie Hung
7c3b4b80ea Fix spacing 2020-02-27 10:17:29 -08:00
Eddie Hung
1ef1ca812b Get rid of (* abc9_{arrival,required} *) entirely 2020-02-27 10:17:29 -08:00
Eddie Hung
a6fec9fe60 abc9_ops: use TimingInfo for -prep_{lut,box} too 2020-02-27 10:17:29 -08:00
Eddie Hung
3ea5506f81 abc9_ops: use TimingInfo for -prep_{lut,box} too 2020-02-27 10:17:29 -08:00
Eddie Hung
cda4acb544 abc9_ops: add and use new TimingInfo struct 2020-02-27 10:17:29 -08:00
Miodrag Milanović
036c46de1e
Merge pull request #1705 from YosysHQ/logger_pass 
Logger pass
 2020-02-26 13:32:49 +01:00
Miodrag Milanovic
1c569fe06a Remove duplicate warning detection 2020-02-23 10:56:27 +01:00
Alberto Gonzalez
f0afd65035
Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes. 2020-02-23 07:22:26 +00:00
Miodrag Milanovic
d079ab9d19 Handle expect no warnings together with expected 2020-02-22 10:52:46 +01:00
Miodrag Milanovic
70db8e9200 Prevent double error message 2020-02-17 16:46:34 +01:00
Miodrag Milanovic
5641b0248f Option to expect no warnings 2020-02-17 15:36:06 +01:00