mirror of
https://github.com/YosysHQ/yosys
synced 2025-08-05 02:40:25 +00:00
TimingInfo: index by (port_name,offset)
This commit is contained in:
parent
7c3b4b80ea
commit
9dcf204dec
2 changed files with 23 additions and 12 deletions
|
@ -25,17 +25,27 @@
|
|||
|
||||
YOSYS_NAMESPACE_BEGIN
|
||||
|
||||
typedef std::pair<RTLIL::SigBit,RTLIL::SigBit> BitBit;
|
||||
|
||||
struct ModuleTiming
|
||||
{
|
||||
RTLIL::IdString type;
|
||||
dict<BitBit, int> comb;
|
||||
dict<RTLIL::SigBit, int> arrival, required;
|
||||
};
|
||||
|
||||
struct TimingInfo
|
||||
{
|
||||
struct NameBit
|
||||
{
|
||||
RTLIL::IdString name;
|
||||
int offset;
|
||||
NameBit() {}
|
||||
NameBit(const RTLIL::SigBit &b) : name(b.wire->name), offset(b.offset) {}
|
||||
bool operator==(const NameBit& nb) const { return nb.name == name && nb.offset == offset; }
|
||||
bool operator!=(const NameBit& nb) const { return !operator==(nb); }
|
||||
unsigned int hash() const { return mkhash_add(name.hash(), offset); }
|
||||
};
|
||||
typedef std::pair<NameBit,NameBit> BitBit;
|
||||
|
||||
struct ModuleTiming
|
||||
{
|
||||
RTLIL::IdString type;
|
||||
dict<BitBit, int> comb;
|
||||
dict<NameBit, int> arrival, required;
|
||||
};
|
||||
|
||||
dict<RTLIL::IdString, ModuleTiming> data;
|
||||
|
||||
TimingInfo()
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue