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Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.

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This commit is contained in:
Alberto Gonzalez 2020-02-23 07:19:52 +00:00
parent 6edca05793
commit f0afd65035
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GPG key ID: 8395A8BA109708B2
9 changed files with 384 additions and 301 deletions
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2
kernel/rtlil.cc
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@ -3924,8 +3924,6 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
cover("kernel.rtlil.sigspec.parse");
AST::current_filename = "input";
AST::use_internal_line_num();
AST::set_line_num(0);
std::vector<std::string> tokens;
sigspec_parse_split(tokens, str, ',');