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https://github.com/YosysHQ/yosys
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Make TimingInfo::TimingInfo(SigBit) constructor explicit
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parent
9dcf204dec
commit
6bb3d9f9c0
3 changed files with 9 additions and 8 deletions
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@ -31,8 +31,9 @@ struct TimingInfo
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{
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RTLIL::IdString name;
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int offset;
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NameBit() {}
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NameBit(const RTLIL::SigBit &b) : name(b.wire->name), offset(b.offset) {}
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NameBit() : offset(0) {}
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NameBit(const RTLIL::IdString name, int offset) : name(name), offset(offset) {}
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explicit NameBit(const RTLIL::SigBit &b) : name(b.wire->name), offset(b.offset) {}
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bool operator==(const NameBit& nb) const { return nb.name == name && nb.offset == offset; }
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bool operator!=(const NameBit& nb) const { return !operator==(nb); }
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unsigned int hash() const { return mkhash_add(name.hash(), offset); }
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@ -127,7 +128,7 @@ struct TimingInfo
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continue;
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}
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for (const auto &d : dst) {
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auto &v = t.arrival[d];
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auto &v = t.arrival[NameBit(d)];
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v = std::max(v, max);
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}
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}
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@ -151,7 +152,7 @@ struct TimingInfo
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continue;
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}
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for (const auto &s : src) {
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auto &v = t.required[s];
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auto &v = t.required[NameBit(s)];
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v = std::max(v, max);
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}
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}
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