mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 09:05:32 +00:00
Code Activity

Merge pull request #1718 from boqwxp/precise_locations

Browse source 
Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
This commit is contained in:
Claire Wolf 2020-03-03 08:38:32 -08:00 • committed by GitHub
commit b597f85b13
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
11 changed files with 388 additions and 305 deletions
Download patch file Download diff file Expand all files Collapse all files

2
kernel/rtlil.cc
View file

@ -3924,8 +3924,6 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
cover("kernel.rtlil.sigspec.parse");
AST::current_filename = "input";
AST::use_internal_line_num();
AST::set_line_num(0);
std::vector<std::string> tokens;
sigspec_parse_split(tokens, str, ',');