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Author	SHA1	Message	Date
Emil J. Tywoniak	350385f5a2	check: fix memory bug in $connect	2026-05-22 18:40:16 +02:00
Emil J. Tywoniak	1dc7a69d7f	memory_bram: create blackboxes	2026-05-22 18:40:16 +02:00
Emil J. Tywoniak	19a4c29a0e	Revert "intel: register bram celltypes" ... This reverts commit 16785a7f75.	2026-05-22 18:40:16 +02:00
Emil J. Tywoniak	24d0bf19bc	Revert "tests: use memory -bram-register in tests/bram" ... This reverts commit 24488a7011.	2026-05-22 18:40:15 +02:00
Emil J. Tywoniak	8c4ab49955	Revert "memory: add -bram-register" ... This reverts commit 2bc6ea7f37.	2026-05-22 18:40:01 +02:00
Emil J. Tywoniak	c64be26334	Revert "memory_bram: add -register" ... This reverts commit b4b5093a14.	2026-05-22 18:40:01 +02:00
Emil J. Tywoniak	116931861d	intel_alm: loosen tests	2026-05-22 18:40:01 +02:00
Emil J. Tywoniak	de481b04b8	gowin: loosen tests	2026-05-22 18:40:01 +02:00
Emil J. Tywoniak	09f55abf1a	flatten: disable signorm	2026-05-22 18:40:01 +02:00
Emil J. Tywoniak	bb19205c79	ecp5: loosen tests	2026-05-22 18:40:01 +02:00
Emil J. Tywoniak	87931fbf7d	nexus: loosen tests	2026-05-22 18:40:01 +02:00
Emil J. Tywoniak	41b3dbbc28	xilinx_dsp: signorm compatibility	2026-05-22 18:40:01 +02:00
Emil J. Tywoniak	6fd7f5c02d	pmgen: hold sigmap pointer instead of owning it	2026-05-22 18:40:01 +02:00
Emil J. Tywoniak	394be03d57	equiv_miter: don't copy $input_port	2026-05-22 18:40:01 +02:00
Emil J. Tywoniak	e73b828e07	rtlil_bufnorm: more xlog	2026-05-22 18:40:01 +02:00
Emil J. Tywoniak	451e01d0a4	design: properly switch signorm mode when restoring saved designs	2026-05-22 18:40:01 +02:00
Emil J. Tywoniak	38fab51fc1	equiv_make: don't copy $input_port	2026-05-22 18:40:01 +02:00
Emil J. Tywoniak	7905df89f3	rtlil: fix cloneInto in signorm	2026-05-22 18:40:01 +02:00
Emil J. Tywoniak	754709aa01	rtlil: sigNormalize Module when added to Design in signorm mode	2026-05-22 18:40:00 +02:00
Emil J. Tywoniak	5355a1739e	rtlil_bufnorm: more xlog	2026-05-22 18:39:42 +02:00
Emil J. Tywoniak	9717a558cc	intel: register bram celltypes	2026-05-22 18:39:42 +02:00
Emil J. Tywoniak	d7b6f1c095	rtlil_bufnorm: ignore timing info harder	2026-05-22 18:39:42 +02:00
Emil J. Tywoniak	14eaedace4	gowin: replace positional arguments in cells_sim.v with named	2026-05-22 18:39:42 +02:00
Emil J. Tywoniak	a93faf811a	Revert "techmap: call hierarchy on map files to determine port directions" ... This reverts commit eabbf6d225.	2026-05-22 18:39:42 +02:00
Emil J. Tywoniak	81b99d83f5	hierarchy: tolerance for apparent recursive instances in techmap files	2026-05-22 18:39:42 +02:00
Emil J. Tywoniak	0eb215dd97	techmap: call hierarchy on map files to determine port directions	2026-05-22 18:39:42 +02:00
Emil J. Tywoniak	b7c9c8eea6	tests: use memory -bram-register in tests/bram	2026-05-22 18:39:41 +02:00
Emil J. Tywoniak	67de0c8c9e	memory: add -bram-register	2026-05-22 18:39:05 +02:00
Emil J. Tywoniak	88aa5f190b	memory_bram: add -register	2026-05-22 18:39:05 +02:00
Emil J. Tywoniak	5e313a19a0	ffmerge: initvals signorm compatibility fixup	2026-05-22 18:39:05 +02:00
Emil J. Tywoniak	eb6dd47bd6	timinginfo: special-case $specify2 in signorm invariant	2026-05-22 18:39:04 +02:00
Emil J. Tywoniak	5bfb631085	opt_expr: with -keepdc disable equality optimization rules that break when ports are sigmapped	2026-05-22 18:38:37 +02:00
Emil J. Tywoniak	bd8738de15	connect: remove input ports on conflict	2026-05-22 18:38:37 +02:00
Emil J. Tywoniak	aecc173f83	opt_dff: sigma harder, FfDataSigMapped	2026-05-22 18:38:37 +02:00
Emil J. Tywoniak	7382be6962	ff: add FfDataSigMapped	2026-05-22 18:38:37 +02:00
Emil J. Tywoniak	be7beaf91a	opt_dff: temporarily disable signorm due to muxtree traversal	2026-05-22 18:38:37 +02:00
Emil J. Tywoniak	95eae1aa6d	tests: fix rtlil roundtrip test	2026-05-22 18:38:36 +02:00
Emil J. Tywoniak	21bed1a411	design: fix signorm commit connectivity to design	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	6c2a90affc	cxxrtl: ignore $input_port	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	faa1a1065c	flatten: redo signormalization to work around fanout issue	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	bd437f207f	abstract: fix test signorm	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	4f665d6efc	signorm: disable passes that use rewrite_sigspecs	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	6447a39c0c	aiger: ignore $input_port	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	8267dee75a	check: stitch info about $connect ports together for driver analysis	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	b42136aa8c	signorm: remove $input cells when leaving	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	5c5df513d1	abstract: skip $input_port cells	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	dad6277a25	flatten: skip $input_port cells in template module	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	d541def612	signorm: skip const when fixing fanout	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	68bb5c6b94	signorm: disable in passes that use swap_names	2026-05-22 18:37:58 +02:00
Emil J. Tywoniak	4d2a6f2b7a	opt_expr: fix invert_map	2026-05-22 18:37:58 +02:00