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Code Activity
8716 commits 121 branches 59 tags 45 MiB
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1780 commits

Author SHA1 Message Date
Eddie Hung
c244b27b6d abc9: cleanup 2020-02-10 10:17:23 -08:00
Eddie Hung
2e8d6ec0b0 Remove unnecessary comma 2020-02-07 12:45:07 -08:00
Eddie Hung
affae35847 techmap: fix shiftx2mux decomposition 2020-02-07 11:02:48 -08:00
Marcin Kościelnicki
89adef352f xilinx: Add support for LUT RAM on LUT4-based devices. 
There are multiple other kinds of RAMs supported on these devices, but
RAM16X1D is the only dual-port one.

Fixes #1549
 2020-02-07 09:03:22 +01:00
Marcin Kościelnicki
d48950d92d xilinx: Initial support for LUT4 devices. 
Adds support for mapping logic, including LUTs, wide LUTs, and carry
chains.

Fixes #1547
 2020-02-07 09:03:22 +01:00
Eddie Hung
1f54b0008f
Merge pull request #1685 from dh73/gowin 
Removing cells_sim from GoWin bram techmap
 2020-02-06 20:59:21 -08:00
Marcin Kościelnicki
30854b9c7f xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*. 2020-02-07 01:00:29 +01:00
Marcin Kościelnicki
95c46ccc55 xilinx: Add support for Spartan 3A DSP block RAMs. 
Part of #1550
 2020-02-07 01:00:29 +01:00
Eddie Hung
1784d25f53
Merge pull request #1684 from YosysHQ/eddie/xilinx_arith_map 
Fix/cleanup +/xilinx/arith_map.v
 2020-02-06 13:51:23 -08:00
Diego H
87883f6d88 Removing cells_sim.v from bram techmap pass 2020-02-06 14:38:29 -06:00
Eddie Hung
d625e399cb Fix $lcu -> MUXCY mapping, credit @mwkmwkmwk 2020-02-06 11:25:07 -08:00
Eddie Hung
5ecbc6c7b2 Fix/cleanup +/xilinx/arith_map.v 2020-02-06 11:00:04 -08:00
Eddie Hung
0b0148399c synth_*: call 'opt -fast' after 'techmap' 2020-02-05 18:39:01 -08:00
Eddie Hung
4c1d3a126d shiftx2mux: fix select out of bounds 2020-02-05 16:41:09 -08:00
Eddie Hung
b6a1f627b5 Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux 2020-02-05 10:47:31 -08:00
Eddie Hung
0671ae7d79
Merge pull request #1661 from YosysHQ/eddie/abc9_required 
abc9: add support for required times
 2020-02-05 18:59:40 +01:00
Marcelina Kościelnicka
34d2fbd2f9
Add opt_lut_ins pass. (#1673) 2020-02-03 14:57:17 +01:00
Marcin Kościelnicki
b44d0e041f xilinx: use RAM32M/RAM64M for memories with two read ports 
This fixes inefficient LUT RAM usage for memories with one write
and two read ports (commonly used as register files).
 2020-02-02 14:34:21 +01:00
Claire Wolf
5f53ea2b5b
Merge pull request #1659 from YosysHQ/clifford/experimental 
Add log_experimental() and experimental() API and "yosys -x"
 2020-01-29 15:25:03 +01:00
Eddie Hung
c5971cb16c synth_xilinx: cleanup help 2020-01-28 17:48:43 -08:00
Eddie Hung
0fd64aab25 synth_xilinx: fix help when no active_design; fixes #1664 2020-01-28 17:41:57 -08:00
Marcin Kościelnicki
7e0e42f907 xilinx: Add simulation model for DSP48 (Virtex 4). 2020-01-29 01:40:00 +01:00
Eddie Hung
7939727d14
Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_luts 
Unpermute LUT ordering for ice40/ecp5/xilinx
 2020-01-28 11:55:51 -08:00
Eddie Hung
245b8c4ab6 Fix unresolved conflict from #1573 2020-01-28 10:17:47 -08:00
N. Engelhardt
086c133ea5
Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate 
synth_xilinx: error out if tristate without '-iopad'
 2020-01-28 17:24:54 +01:00
Eddie Hung
e18aeda7ed Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards 
Just like Verilog...
 2020-01-27 14:02:13 -08:00
Eddie Hung
cfb0366a18 Import tests from #1628 2020-01-27 13:56:16 -08:00
Eddie Hung
ce6a690d27 xilinx/ice40/ecp5: undo permuting LUT masks in lut_map 
Now done in read_aiger
 2020-01-27 13:30:27 -08:00
Eddie Hung
48f3f5213e
Merge pull request #1619 from YosysHQ/eddie/abc9_refactor 
Refactor `abc9` pass
 2020-01-27 13:29:15 -08:00
Eddie Hung
f2576c096c Merge branch 'eddie/abc9_refactor' into eddie/abc9_required 2020-01-27 12:29:28 -08:00
Eddie Hung
af8281d2f5
Merge pull request #1656 from YosysHQ/eddie/ice40_abc9_warnings 
ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
 2020-01-27 09:54:04 -08:00
Claire Wolf
cef607c8b7 Add log_experimental() and experimental() API and "yosys -x" 
Signed-off-by: Claire Wolf <clifford@clifford.at>
 2020-01-27 18:27:47 +01:00
Eddie Hung
81e6b040a4 ice40: add SB_SPRAM256KA arrival time 2020-01-24 12:17:09 -08:00
Eddie Hung
b178761551 ice40: reduce ABC9 internal fanout warnings with a param for CI->I3 2020-01-24 11:59:48 -08:00
Eddie Hung
7858cf20a9 Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0 2020-01-23 19:02:27 -08:00
Eddie Hung
da134701cd Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0 2020-01-22 14:22:03 -08:00
Eddie Hung
72e4540ca9 Explicitly create separate $mux cells 2020-01-21 16:49:34 -08:00
Eddie Hung
3d9737c1bd Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-21 16:27:40 -08:00
Eddie Hung
152dfd3dd4 Fix tests -- when Y_WIDTH is non-pow-2 2020-01-21 15:19:41 -08:00
Eddie Hung
8d1b736c4f Move from +/shiftx2mux.v into +/techmap.v; cleanup 2020-01-21 15:19:41 -08:00
Eddie Hung
7977574995 New techmap +/shiftx2mux.v which decomposes LSB first; better for ABC 2020-01-21 15:19:41 -08:00
Eddie Hung
b7be6cfd65
Merge pull request #1643 from YosysHQ/eddie/cleanup_arith_map 
Cleanup +/xilinx/arith_map.v
 2020-01-18 09:11:52 -08:00
David Shah
a4cfd1237f
Merge pull request #1602 from niklasnisbeth/ice40-init-vals-warning 
ice40: Demote conflicting FF init values to a warning
 2020-01-18 09:47:17 +00:00
Eddie Hung
78ffd5d193 synth_ice40: call wreduce before mul2dsp 2020-01-17 15:41:55 -08:00
Eddie Hung
5c589244df Deprecate `_CLB_CARRY from +/xilinx/arith_map.v since #1623 2020-01-17 12:02:46 -08:00
Eddie Hung
1e6d56dca1 +/xilinx/arith_map.v fix $lcu rule 2020-01-17 11:28:37 -08:00
Eddie Hung
b0605128b6 Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required 2020-01-15 16:42:27 -08:00
Eddie Hung
03ce2c72bb Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-15 16:42:16 -08:00
Eddie Hung
5a63c19747 abc9_ops: -write_box is empty, output a dummy box to prevent ABC error 2020-01-15 13:14:48 -08:00
Miodrag Milanović
abba1541bc
Merge pull request #1636 from YosysHQ/eddie/fix_synth_xilinx_W 
synth_xilinx: fix default W value for non-xc7
 2020-01-15 08:47:16 +01:00